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XDPS21071XUMA1

反激 稳压器 正 输出 升压/降压 - DC DC 切换控制器 IC PG-DSO-12-20

产品类别:半导体    多通道IC(PMIC)   

制造商:Infineon(英飞凌)

官网地址:http://www.infineon.com/

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XDPS21071XUMA1概述
Infineon XDPS21071 是业内首款回扫控制器 ic 、用于在初级侧引入 zvs (零电压切换)、通过简化电路和经济型开关实现高效率。通过驱动外部低电压开关以诱使负电流放电主高电压 mosfet 、与传统的谷底切换类型的开关方案相比、切换损耗可进一步降低。

高密度、具有高切换频率
高效 Adaptive zvs 操作和频率定律、用于可变输出设计
通过 dcm 操作、安全可靠地操作 sr
采用双集成栅极驱动器和启动单元、设计简单
易于使用 GUI 工具进行配置设计
XDPS21071XUMA1规格参数
参数名称
属性值
类别
半导体;多通道IC(PMIC)
厂商名称
Infineon(英飞凌)
包装
卷带(TR)剪切带(CT)
输出类型
晶体管驱动器
功能
升压/降压
输出配置
拓扑
反激
输出数
1
输出阶段
1
电压 - 供电 (Vcc/Vdd)
3.3V
频率 - 开关
24.9kHz ~ 139.4kHz
同步整流器
时钟同步
控制特性
限流,软启动
工作温度
-25°C ~ 125°C(TJ)
安装类型
表面贴装型
封装/外壳
16-SOIC(0.154",3.90mm 宽),12 引线
供应商器件封装
PG-DSO-12-20
基本产品编号
XDPS21071
XDPS21071XUMA1文档预览
XDPS21071
Forced Frequency Resonant Flyback controller
Based on FW: REV 1.0
Product Highlights
Integrated 600 V startup cell for fast startup and direct bus voltage sensing
Multi-mode operation with forced frequency resonant mode (FFR)
DCM operation guaranteed
Adaptive current limitation for variable Vout
Supports low no load input power to meet stringent regulatory standard
One pin UART interface for configuration
Features
Multi-mode operation with BM, DCM
Configurable ZVS enabled line voltage
ZVS gate drive signal for forced resonant mode
Built-in soft-start
Built-in protection modes
Brown-in and brownout detection via integrated HV
startup cell
Pb-free lead plating; RoHS compliant
Halogen-free according to IEC61249-2-21
Description
The XDPS21071 is a digital PWM controller for high density
adapter applications based on DCM flyback topology. A wide
feature set is provided in a DSO-12 package and requires
only a minimum of external components. An integrated
ASSP digital engine provides advanced algorithms for multi-
mode operation and protection features. A forced frequency
resonant operation support optimized high density adapter
system dimensioning. In addition a one-time-
programmable (OTP) unit is integrated to provide a
selective set of configurable parameters, which can be
matched to a dedicated system design.
Applications
High density adapter/charger
Qualified for industrial applications according to the
relevant tests of JEDEC47/20/22
85 ... 264 VAC
Product Validation
VCC
HV
GPIO
ZCD
GD1
GD0
XDPS21071
CS
MFIO
GND
Figure 1
Marking
XDPS21071
Typical application
Package
PG-DSO-12-20
FW Revision
REV 1.0
SP Ordering Code
SP005355100
Data Sheet
Please read the Important Notice and Warnings at the end of this document
www.infineon.com
Revision 2.0
2019-10-30
Forced Frequency Resonant Flyback controller
Table of contents
Description
Table of contents
Description
Description
Based on FW: REV 1.0 ...................................................................................................................... 1
Product Highlights .......................................................................................................................... 1
Description
Features 1
Applications ................................................................................................................................... 1
Description
Product Validation .......................................................................................................................... 1
Description 1
Table of contents ............................................................................................................................ 2
1
2
3
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.5.1
4.1.5.2
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.1.3
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.8.1
4.2.9
4.2.10
4.2.10.1
4.2.10.2
4.2.11
4.2.12
4.2.13
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
Data Sheet
Pin Configuration and Functionality ................................................................................ 4
Representative Block Diagram ........................................................................................ 5
Introduction.................................................................................................................. 6
Functional Description ................................................................................................... 7
Power supply management .................................................................................................................... 7
VCC capacitor charge-up and startup sequence............................................................................... 7
Brown-in monitoring.......................................................................................................................... 8
Brown-out protection response ........................................................................................................ 9
During burst mode operation ........................................................................................................... 9
Bang-bang mode during latched and auto-restart operation ....................................................... 10
During latched operation............................................................................................................ 11
During auto-restart operation .................................................................................................... 11
Control features..................................................................................................................................... 12
Reflected voltage sensing and Vcs offset calculation based on output voltage............................ 14
Output voltage sensing via ZCD pin ........................................................................................... 15
Ringing suppression time ........................................................................................................... 17
Vcs offset calculation based on output voltage sensed at ZCD pin .......................................... 17
Vbulk voltage measurement via HV startup cell ............................................................................. 18
Propagation delay compensation (PDC) ......................................................................................... 18
Soft-start........................................................................................................................................... 20
Leading edge blanking (LEB) at CS pin ............................................................................................ 20
Spike blanking at CS pin for 2nd level over-current detection (OCP2) .......................................... 21
Gate driver output GD0 and GD1 ..................................................................................................... 21
Multi-mode operation ...................................................................................................................... 22
Frequency law setting for XDPS21071 ........................................................................................ 24
Frequency jittering ........................................................................................................................... 25
Burst mode operation ...................................................................................................................... 26
Burst mode entry ........................................................................................................................ 27
Burst operation ........................................................................................................................... 27
Burst mode exit ................................................................................................................................ 28
Forced frequency resonant (FFR) mode operation......................................................................... 28
UART function at GPIO pin ............................................................................................................... 30
Protection features ............................................................................................................................... 30
Auto-Restart Mode (ARM) ................................................................................................................. 31
Latch Mode (LM) ............................................................................................................................... 31
VCC Under-Voltage lockout (UVOFF) ............................................................................................... 31
Brown-In Protection (BIP) ................................................................................................................ 31
Brown-Out Protection (BOP) ........................................................................................................... 32
Over-Current Protection level 1 (OCP1) .......................................................................................... 32
2
Revision 2.0
2019-10-30
Forced Frequency Resonant Flyback controller
Table of contents
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
4.3.13
5
5.1
5.2
5.2.1
6
6.1
6.2
6.3
6.4
6.5
7
7.1
7.2
8
9
9.1
10
Over-Current Protection level 2 (OCP2) .......................................................................................... 32
High input at CS pin (CShigh) .......................................................................................................... 32
MFIO pin high (MFIOH) ..................................................................................................................... 32
Internal over-temperature detection (IntOTP) ............................................................................... 32
Primary side output Over-Voltage Protection (VoutOVP)............................................................... 33
Over load power protection............................................................................................................. 33
CS pin short protection .................................................................................................................... 33
Configuration ............................................................................................................... 34
Overview of configurable parameters using .dp Vision ....................................................................... 34
Overview of configurable parameters and functions .......................................................................... 34
Configurable parameters and functions ......................................................................................... 34
Electrical Characteristics ............................................................................................... 36
Definitions ............................................................................................................................................. 36
Absolute Maximum Ratings .................................................................................................................. 36
Package Characteristics ........................................................................................................................ 37
Operating Range.................................................................................................................................... 38
Characteristics ....................................................................................................................................... 39
Package Information ..................................................................................................... 48
Outline dimensions ............................................................................................................................... 48
Footprint and packing........................................................................................................................... 49
Marking ....................................................................................................................... 50
Appendix ..................................................................................................................... 51
Minimum required capacitive load at GD0 and GD1 pin ...................................................................... 51
References ................................................................................................................... 52
Revision history............................................................................................................................. 53
Data Sheet
3
Revision 2.0
2019-10-30
Forced Frequency Resonant Flyback controller
Pin Configuration and Functionality
1
Pin Configuration and Functionality
The pin configuration is shown in Figure 2 and the functions are described in Table 1.
ZCD
MFIO
GPIO
1
2
12
11
GND
VCC
GD0
XDPS21071
3
4
10
9
CS
GD1
HV
5
6
8
7
HV
HV
HV
PG-DSO-12-20
Figure 2
Table 1
Pin Configuration of XDPS21071
Pin Definitions and Functions
Pin
1
Type
I
Zero Crossing Detection
ZCD pin is connected to an auxiliary winding for zero crossing detection and positive
pin voltage measurement.
Symbol
ZCD
Function
MFIO
2
I
Multi-Functional Input Output
MFIO pin is connected to an optocoupler that provides an amplified error signal for
the PWM mode operation.
GPIO
3
IO
CS
4
I
HV
5, 6, 7, 8 I
GD1
9
I
GD0
VCC
GND
10
11
12
O
I
O
Digital General Purpose Input Output
GPIO pin provides an UART interface until brown-in. It is switched to weak
pull down mode and disabled UART function during normal operation.
Current Sense
CS pin is connected via a resistor in series to an external shunt resistor and
the source of the power MOSFET.
High Voltage Input
HV pin is connected to the rectified bulk voltage. An internally connected 600
V HV startup-cell is used for initial VCC charge. Furthermore brown-in and
brownout detection is provided.
FFR Signal Gate Driver Output
GD1 pin provides a gate driver pulse signal to initiate the forced frequency
resonant mode operation.
Gate Driver Output
Output for directly driving the main power MOSFET.
Positive Voltage Supply
IC power supply.
Power and Signal Ground
Data Sheet
4
Revision 2.0
2019-10-30
Forced Frequency Resonant Flyback controller
Representative Block Diagram
2
Representative Block Diagram
Figure 3 shows a simplified top level block diagram of the IC functionality.
HV
XDPS21071
HV Startup-cell
Closed/Open
Startup-Cell
Driver
Vbulk Brown-out
Protection
I
HVBO
= 0.443 mA
Bang-Bang Ctrl
V
VCCBBoff
= 20.5 V
V
VCCBBonAR/LM
= 9 V
Q
M
D1
Vbulk
measurement
R
M
Vbulk Brown-in
Protection
I
HVBI
= 1.15 mA
Overtemperature
Detection
&
T
JOTP
= 130 °C
VCC
VCC Brown-in
Protection
V
VCCBI
= 9.1 V
UVLO
V
VCCon
= 20.5 V
HW Reset
Protection
Modes
V
VCCoffx
= 7.2 V / 9.6 V
Power
Management
Auto Restart
Mode
Latch
Mode
ZCD
1k
Vout reflected Voltage
Measurement
Vout OV
Protection
V
ZCDOVP
= 2.75 V
Soft-Start
Open Loop Timer
t
MFIOH
= 31.3 ms
Frequency clamp
f
SW
Frequency Law
FFR Mode
With ZVS Pulse
Generation
PWM
Logic
Gate Driver
GD0
V
MFIOH
= 2.41 V
C2
V
CSPK
V
MFIO
PDC
V
VDDP
= 3.3 V
V
MFIO
R
MFIOPU
Burst Mode Function
MFIO
V
MFIOBMEX1
C3
Gate Driver
GD1
Vcs_offset
BM Exit
V
MFIOBMWK
C5
on-phase
V
MFIOBMPA
V
MFIOBMEN
C6
off-phase
BM 2-point
Regulation
BM Ctrl
C7
BM Entry
Cycle by Cycle Peak Current Ctrl
CS
1k
10k
1 pF
OCP1
V
CSPK
t
CSLEB
2nd Level Overcurrent Detection
OCP2
Auto Restart
Input Detection
t
CSOCP2BL
V
CSOCP2
= 0.8 V
V
VDDP
= 3.3 V
I
GPIOLPU
GPIO
UART
Communication
Parameter
Configuration
Figure 3
Representative Block Diagram of XDPS21071
Data Sheet
5
Revision 2.0
2019-10-30
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