dsPIC33CH512MP508 FAMILY
48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers
with High-Resolution PWM and CAN Flexible Data-Rate (CAN FD)
Operating Conditions
• 3V to 3.6V, -40°C to +125°C:
- Master Core: DC to 90 MIPS
- Slave Core: DC to 100 MIPS
• 3V to 3.6V, -40°C to +150°C:
- Master Core: DC to 60 MIPS
- Slave Core: DC to 60 MIPS
Power Management
• Low-Power Management Modes (Sleep, Idle,
Doze)
• Integrated Power-on Reset and Brown-out Reset
High-Resolution PWM with Fine Edge
Placement
• Up to Twelve PWM Channels:
- Four channels for Master
- Eight channels for Slave
• 250 ps PWM Resolution
• Applications Include:
- DC/DC Converters
- AC/DC power supplies
- Uninterruptable Power Supply (UPS)
- Motor Control: BLDC, PMSM, SR, ACIM
Core: Dual 16-Bit dsPIC33CH CPU
• Master/Slave Core Operation
• Independent Peripherals for Master Core and
Slave Core
• Configurable Shared Resources for Master Core
and Slave Core
• Master Core with 256-512 Kbytes of Program
Flash with ECC and 32-48K Data RAM with BIST
• Slave Core with 72 Kbytes of Program RAM (PRAM)
with ECC and 16K Data RAM with BIST
• Fast 6-Cycle Divide
• LiveUpdate
• Message Boxes and FIFO to Communicate
Between Master and Slave (MSI)
• Code Efficient (C and Assembly) Architecture
• 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle, Mixed-Sign MUL Plus Hardware
Divide
• 32-Bit Multiply Support
• Five Sets of Interrupt Context Selected Registers
per Core for Fast Interrupt Response
• Zero Overhead Looping
Timers/Output Compare/Input Capture
• Two General Purpose 16-Bit Timers:
- One each for Master and Slave
• Peripheral Trigger Generator (PTG) Module:
- One module for Master
- Slave can interrupt on select PTG sources
- Useful for automating complex sequences
• Twelve SCCP Modules:
- Eight modules for Master
- Four modules for Slave
- Timer, Capture/Compare and PWM modes
- 16 or 32-bit time base
- 16 or 32-bit capture
- 4-deep capture buffer
- Fully asynchronous operation, available in
Sleep modes
Clock Management
• Internal Oscillator
• Programmable PLLs and Oscillator Clock
Sources
• Master Reference Clock Output
• Slave Reference Clock Output
• Fail-Safe Clock Monitor (FSCM)
• Fast Wake-up and Start-up
• Backup Internal Oscillator
• LPRC Oscillator
2018-2019 Microchip Technology Inc.
DS70005371D-page 1
dsPIC33CH512MP508 FAMILY
Advanced Analog Features
• Four ADC Modules:
- One module for Master core
- Three modules for Slave core
- 12-bit, 3.25 Msps ADC
- Up to 18 conversion channels
- 250 ns conversion latency
• Four DAC/Analog Comparator Modules:
- One module for Master core
- Three modules for Slave core
- 12-bit DACs with hardware slope
compensation
- 15 ns analog comparators
• Three PGA Modules:
- Three modules for Slave core
- Can be read by Master ADC
• Shared DAC/Analog Output:
- DAC/analog comparator outputs
- PGA outputs
Direct Memory Access (DMA)
• Eight DMA Channels:
- Six DMA channels available for the Master core
- Two DMA channels available for the Slave core
Debugger Development Support
• In-Circuit and In-Application Programming
• Simultaneous Debugging Support for Master and
Slave Cores
• Master Only Debug and Slave Only Debug
Support
• Master with Three Complex, Five Simple
Breakpoints and Slave with One Complex,
Two Simple Breakpoints
• IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Trace Buffer and Run-Time Watch
Safety Features
•
•
•
•
•
•
•
•
•
•
•
•
DMT (Deadman Timer)
ECC (Error Correcting Code)
WDT (Watchdog Timer)
CodeGuard™ Security
CRC (Cyclic Redundancy Check)
ICSP™ Write Inhibit
RAM Memory Built-In Self Test (MBIST)
Two-Speed Start-up
Fail-Safe Clock Monitoring (FSCM)
Backup FRC (BFRC)
Capless Internal Voltage Regulator
Virtual Pins for Redundancy and Monitoring
Communication Interfaces
• Three UART Modules:
- Two modules for Master core
- One module for Slave core
- Support for DMX, LIN/J2602 protocols
• Three 4-Wire SPI/I
2
S Modules:
- Two modules for Master core
- One module for Slave core
• Two CAN Flexible Data-Rate (FD) Modules for the
Master Core
• Three I
2
C Modules:
- Two modules for Master
- One module for Slave
- Support for SMBus
• PPS to Allow Function Remap
• Programmable Cyclic Redundancy Check (CRC)
for the Master
• Two SENT Modules for the Master
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1: -40°C to +125°C)
Compliant
• Class B Safety Library, IEC 60730
DS70005371D-page 2
2018-2019 Microchip Technology Inc.
dsPIC33CH512MP508 FAMILY
TABLE 1:
Core Frequency
Program Memory
Internal Data RAM
16-Bit Timer
DMA
SCCP (Capture/Compare/Timer)
UART
SPI/I
2
S
I
2
C
CAN FD
SENT
CRC
CVD
QEI
PTG
CLC
16-Bit High-Speed PWM
12-Bit ADC
Digital Comparator
12-Bit DAC/Analog CMP Module
Watchdog Timer
Deadman Timer
Input/Output
Simple Breakpoints
PGAs
(1)
MASTER AND SLAVE CORE FEATURES
(2)
Feature
Master Core
90 MIPS @ 180 MHz
256K-512 Kbytes
32-48 Kbytes
1
6
8
2
2
2
2
2
1
1
1
1
4
4
1
4
1
1
1
69
5
—
—
—
Slave Core
100 MIPS @ 200 MHz
72 Kbytes (PRAM)
16 Kbytes
1
2
4
1
1
1
—
—
—
1
1
—
4
8
3
4
3
1
1
69
2
3
—
—
Shared
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
69
—
3
1
1
DAC Output Buffer
Oscillator
Note 1:
Slave owns this peripheral/feature, but it is shared with the Master.
2:
Module instances shown in
Table 1
are for dsPIC33CHXXXMPX08 devices. For device variant information, see
Table 2.
2018-2019 Microchip Technology Inc.
DS70005371D-page 3
dsPIC33CH512MP508 PRODUCT FAMILIES
The device names, pin counts, memory sizes and peripheral availability of each device are listed in
Table 2.
The following pages show their pinout diagrams.
12-Bit DAC/Analog CMP
PWM (High Resolution)
Current Bias Source
ADC Channels
Flash/(PRAM)
ADC Modules
16-Bit Timers
Data RAM
CAN FD
SPI/I
2
S
SCCP
UART
Product
Core
Devices with CAN FD
dsPIC33CH256MP505
dsPIC33CH512MP505
dsPIC33CH256MP506
dsPIC33CH512MP506
dsPIC33CH256MP508
dsPIC33CH512MP508
2018-2019 Microchip Technology Inc.
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
48
48
64
64
80
80
256K
(72K)
512K
(72K)
256K
(72K)
512K
(72K)
256K
(72K)
512K
(72K)
32K
16K
48K
16K
32K
16K
48K
16K
32K
16K
48K
16K
1
3
1
3
1
3
1
3
1
3
1
3
16
15
16
15
16
18
16
18
16
18
16
18
1
1
1
1
1
1
1
1
1
1
1
1
8
4
8
4
8
4
8
4
8
4
8
4
2
—
2
—
2
—
2
—
2
—
2
—
2
—
2
—
2
—
2
—
2
—
2
—
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
4
4
4
4
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
4
8
4
8
4
8
4
8
4
8
4
8
1
3
1
3
1
3
1
3
1
3
1
3
—
3
—
3
—
3
—
3
—
3
—
3
1
—
1
—
1
—
1
—
1
—
1
—
REFO
SENT
PGA
CRC
Pins
PTG
CLC
QEI
I
2
C
DS70005371D-page 4
dsPIC33CH512MP508 FAMILY
TABLE 2:
dsPIC33CH512MP508 MOTOR CONTROL/POWER SUPPLY FAMILIES
1
1
1
1
1
1
1
1
1
1
1
1
2018-2019 Microchip Technology Inc.
DS70005371D-page 5
TABLE 3:
dsPIC33CH512MP208 MOTOR CONTROL/POWER SUPPLY FAMILIES WITH NO CAN FD
12-Bit DAC/Analog CMP
PWM (High Resolution)
Current Bias Source
1
—
1
—
1
—
1
—
1
—
1
—
ADC Channels
Flash/(PRAM)
ADC Modules
16-Bit Timers
Data RAM
CAN FD
SPI/I
2
S
SCCP
UART
Product
Core
Devices with No CAN FD
dsPIC33CH256MP205
dsPIC33CH512MP205
dsPIC33CH256MP206
dsPIC33CH512MP206
dsPIC33CH256MP208
dsPIC33CH512MP208
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
48
48
64
64
80
80
256K
(72K)
512K
(72K)
256K
(72K)
512K
(72K)
256K
(72K)
512K
(72K)
32K
16K
48K
16K
32K
16K
48K
16K
32K
16K
48K
16K
1
3
1
3
1
3
1
3
1
3
1
3
16
15
16
15
16
18
16
18
16
18
16
18
1
1
1
1
1
1
1
1
1
1
1
1
8
4
8
4
8
4
8
4
8
4
8
4
—
—
—
—
—
—
—
—
—
—
—
—
2
—
2
—
2
—
2
—
2
—
2
—
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
4
4
4
4
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
4
8
4
8
4
8
4
8
4
8
4
8
1
3
1
3
1
3
1
3
1
3
1
3
—
3
—
3
—
3
—
3
—
3
—
3
1
1
1
1
1
1
1
1
1
1
1
1
REFO
SENT
PGA
CRC
Pins
PTG
CLC
QEI
I
2
C
dsPIC33CH512MP508 FAMILY