在0.35 μm硅衬底CMOS工艺条件下，分析了集成平面电感器的单片DC/DC变换器的功率损耗，折中考虑了设计中的难点以及各种影响因素。优化了变换器的转换效率，确定其开关频率为100 MHz；考虑片上集成平面电感器的单位面积电感值与品质因数的大小也是决定DC/DC变换器性能的关键因素，该文给出了双层平面螺旋电感器的物理设计与几何参数优化，获得了双层平面螺旋电感。模拟结果表明该变换器工作稳定，转换效率可以达到62%。关 键 词 DC/DC变换器; 转换效率; 单片; 平面电感器Abstract The challenges and tradeoffs in designing a monolithic DC/DC converter including planner inductor using 0.35 μm CMOS technology on silicon substrate are described by analyzing the power dissipation of the converters. The efficiency of the converter is optimized. The physical design and geometric parameters optimization of the desired planar inductor are given. A double-layer spiral inductor with quality factor of 2.3, area of 0.38 square millimeters, inductance of 35 nH are obtained. From the simulated results, a steady Buck converter with the efficiency of 62% is achieved.Key words DC/DC converter; efficiency; monolithic; planar inductor