STM32F10X硬件8MHz改为24MHz软件配置修改方法

1、单片机为STM32F103最快运行速度72MHz，系统默认使用8MHz外部时钟晶振，如果硬件采用24MHz晶振，软件就需要修改时钟配置，修改方法如下，我们用的硬件为STM32F10X_MD，并不是STM32F10X_CL，在static void SetSysClockTo72(void)函数中：
#ifdef STM32F10X_CL
    // Configure PLLs ------------------------------------------------------
    // PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz
    // PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz
       
    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
 
    // Enable PLL2
    RCC->CR |= RCC_CR_PLL2ON;
    // Wait till PLL2 is ready
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
 
    // PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
                            RCC_CFGR_PLLMULL9);
#else   
    //  PLL configuration: PLLCLK = HSE * 9 = 72 MHz
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
                                        RCC_CFGR_PLLMULL));
    //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL3);
#endif // STM32F10X_CL


2、单片机为STM32F100最快运行速度24MHz，系统默认使用8MHz外部时钟晶振，如果硬件采用24MHz晶振，软件就需要修改时钟配置，修改方法如下，我们用的硬件为STM32F10X_MD_VL，并不是STM32F10X_CL，在static void SetSysClockTo24(void)函数中：
#ifdef STM32F10X_CL
    // Configure PLLs ------------------------------------------------------
    // PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
                            RCC_CFGR_PLLMULL6);

    // PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz
    // PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz       
    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
 
    // Enable PLL2
    RCC->CR |= RCC_CR_PLL2ON;
    // Wait till PLL2 is ready
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }  
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
    //  PLL configuration:  = (HSE / 2) * 6 = 24 MHz
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
    //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);  //8MHz外部晶振
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL3);    //24MHz外部晶振
#else   
    //  PLL configuration:  = (HSE / 2) * 6 = 24 MHz
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
    //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);          //8MHz外部晶振
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL3);            //24MHz外部晶振
#endif // STM32F10X_CL


3、修改MDK编译环境
     把原本编译STM32F103的keil工程修改为STM32F100的工程需要修改工程配置，如下：