MC9S12XS128 MAL BootLoader（2）

用户程序就按照正常程序写即可，需要注意以下几点

程序写入固定的位置，不能和BootLoader程序的位置重合，否则有可能程序无法经过BootLoader下载后运行，同样也是在prm中进行相应的操作；

需要用到中断的，要对中断向量进行偏移；

对起始向量进行偏移；

写入地址对齐。

1.BootLoader程序写入固定位置：

ROM_C000      = READ_ONLY   DATA_NEAR IBCC_NEAR  0xC000 TO   0xEFDF;

确保不会和BootLoader的F000开始的地址重合；

INTO  ROM_C000/*, ROM_4000*/;

2.对中断向量进行偏移，中断发生时，将当前PC位置压入堆栈中，然后通过中断向量找到当前中断函数，一个中断向量不能对应两个中断函数地址；

中断向量的偏移，首先要定义如下的中断向量表，其中对于不用的中断用Unimplemented_ISR表示，再在main函数中令中断偏移寄存器IVBR=0x7F。

3.起始向量的偏移，起始向量即程序最开始PC指针要指向的地址，默认为FFFE，如果偏移，那么该程序是没法直接运行的，只有在BootLoader中运行，所以我们是在使用上位机发送该程序S19文件时，需要将FFFE这一行中的FFFE改为我们需要的地址。

4．在使用上位机传输S19文件时，有部分地址是与FLASH写操作地址不对齐的，比如FFFE，那么需要我们补齐FFF0~FFFD地址的数据为FF；

#pragma CODE_SEG NON_BANKED

interrupt void Unimplemented_ISR(void)

{

  asm BGND; //software breakpoint

}

#pragma CODE_SEG DEFAULT

typedef void (*near tIsrFunc)(void);

const tIsrFunc VectorTable[] @0xEF10 =

{

  Unimplemented_ISR,    // Vector base + 0x10   Spurious interrupt

  Unimplemented_ISR,    // Vector base + 0x12   System Call Interrupt (SYS)

  Unimplemented_ISR,    // Vector base + 0x14   Reserved

  Unimplemented_ISR,    // Vector base + 0x16   Reserved

  Unimplemented_ISR,    // Vector base + 0x18   Reserved

  Unimplemented_ISR,    // Vector base + 0x1A   Reserved

  Unimplemented_ISR,    // Vector base + 0x1C   Reserved

  Unimplemented_ISR,    // Vector base + 0x1E   Reserved

  Unimplemented_ISR,    // Vector base + 0x20   Reserved

  Unimplemented_ISR,    // Vector base + 0x22   Reserved

  Unimplemented_ISR,    // Vector base + 0x24   Reserved

  Unimplemented_ISR,    // Vector base + 0x26   Reserved

  Unimplemented_ISR,    // Vector base + 0x28   Reserved

  Unimplemented_ISR,    // Vector base + 0x2A   Reserved

  Unimplemented_ISR,    // Vector base + 0x2C   Reserved

  Unimplemented_ISR,    // Vector base + 0x2E   Reserved

  Unimplemented_ISR,    // Vector base + 0x30   Reserved

  Unimplemented_ISR,    // Vector base + 0x32   Reserved

  Unimplemented_ISR,    // Vector base + 0x34   Reserved

  Unimplemented_ISR,    // Vector base + 0x36   Reserved

  Unimplemented_ISR,    // Vector base + 0x38   Reserved

  Unimplemented_ISR,    // Vector base + 0x3A   Reserved

  Unimplemented_ISR,    // Vector base + 0x3C   Reserved

  Unimplemented_ISR,    // Vector base + 0x3E   ATD0 Compare Interrupt

  Unimplemented_ISR,    // Vector base + 0x40   Reserved

  Unimplemented_ISR,    // Vector base + 0x42   Reserved

  Unimplemented_ISR,    // Vector base + 0x44   Reserved

  Unimplemented_ISR,    // Vector base + 0x46   Reserved

  Unimplemented_ISR,    // Vector base + 0x48   Reserved

  Unimplemented_ISR,    // Vector base + 0x4A   Reserved

  Unimplemented_ISR,    // Vector base + 0x4C   Reserved

  Unimplemented_ISR,    // Vector base + 0x4E   Reserved

  Unimplemented_ISR,    // Vector base + 0x50   Reserved

  Unimplemented_ISR,    // Vector base + 0x52   Reserved

  Unimplemented_ISR,    // Vector base + 0x54   Reserved

  Unimplemented_ISR,    // Vector base + 0x56   Reserved

  Unimplemented_ISR,    // Vector base + 0x58   Reserved

  Unimplemented_ISR,    // Vector base + 0x5A   Reserved

  Unimplemented_ISR,    // Vector base + 0x5C   Reserved

  Unimplemented_ISR,    // Vector base + 0x5E   Reserved

  Unimplemented_ISR,    // Vector base + 0x60   Reserved

  Unimplemented_ISR,    // Vector base + 0x62   Reserved

  Unimplemented_ISR,    // Vector base + 0x64   Reserved

  Unimplemented_ISR,    // Vector base + 0x66   Reserved

  Unimplemented_ISR,    // Vector base + 0x68   Reserved

  Unimplemented_ISR,    // Vector base + 0x6A   Reserved

  Unimplemented_ISR,    // Vector base + 0x6C   Reserved

  Unimplemented_ISR,    // Vector base + 0x6E   Reserved

  Unimplemented_ISR,    // Vector base + 0x70   Reserved

  Unimplemented_ISR,    // Vector base + 0x72   Reserved

  Unimplemented_ISR,    // Vector base + 0x74   Periodic interrupt timer channel 3

  Unimplemented_ISR,    // Vector base + 0x76   Periodic interrupt timer channel 2

  Unimplemented_ISR,    // Vector base + 0x78   Periodic interrupt timer channel 1

  PIT0_ISR,             // Vector base + 0x7A   Periodic interrupt timer channel 0

  Unimplemented_ISR,    // Vector base + 0x7C   High Temperature Interrupt (HTI)

  Unimplemented_ISR,    // Vector base + 0x7E   Autonomous periodical interrupt (API)

  Unimplemented_ISR,    // Vector base + 0x80   Low-voltage interrupt (LVI)

  Unimplemented_ISR,    // Vector base + 0x82   Reserved

  Unimplemented_ISR,    // Vector base + 0x84   Reserved

  Unimplemented_ISR,    // Vector base + 0x86   Reserved

  Unimplemented_ISR,    // Vector base + 0x88   Reserved

  Unimplemented_ISR,    // Vector base + 0x8A   Reserved

  Unimplemented_ISR,    // Vector base + 0x8C   PWM emergency shutdown

  Unimplemented_ISR,    // Vector base + 0x8E   Port P Interrupt

  Unimplemented_ISR,    // Vector base + 0x90   Reserved

  Unimplemented_ISR,    // Vector base + 0x92   Reserved

  Unimplemented_ISR,    // Vector base + 0x94   Reserved

  Unimplemented_ISR,    // Vector base + 0x96   Reserved

  Unimplemented_ISR,    // Vector base + 0x98   Reserved

  Unimplemented_ISR,    // Vector base + 0x9A   Reserved

  Unimplemented_ISR,    // Vector base + 0x9C   Reserved

  Unimplemented_ISR,    // Vector base + 0x9E   Reserved

  Unimplemented_ISR,    // Vector base + 0xA0   Reserved

  Unimplemented_ISR,    // Vector base + 0xA2   Reserved

  Unimplemented_ISR,    // Vector base + 0xA4   Reserved

  Unimplemented_ISR,    // Vector base + 0xA6   Reserved

  Unimplemented_ISR,    // Vector base + 0xA8   Reserved

  Unimplemented_ISR,    // Vector base + 0xAA   Reserved

  Unimplemented_ISR,    // Vector base + 0xAC   Reserved

  Unimplemented_ISR,    // Vector base + 0xAE   Reserved

  Unimplemented_ISR,    // Vector base + 0xB0   CAN0 transmit

  Unimplemented_ISR,    // Vector base + 0xB2   CAN0 receive

  Unimplemented_ISR,    // Vector base + 0xB4   CAN0 errors

  Unimplemented_ISR,    // Vector base + 0xB6   CAN0 wake-up

  Unimplemented_ISR,    // Vector base + 0xB8   FLASH

  Unimplemented_ISR,    // Vector base + 0xBA   FLASH Fault Detect

  Unimplemented_ISR,    // Vector base + 0xBC   Reserved

  Unimplemented_ISR,    // Vector base + 0xBE   Reserved

  Unimplemented_ISR,    // Vector base + 0xC0   Reserved

  Unimplemented_ISR,    // Vector base + 0xC2   Reserved

  Unimplemented_ISR,    // Vector base + 0xC4   CRG self-clock mode

  Unimplemented_ISR,    // Vector base + 0xC6   CRG PLL lock

  Unimplemented_ISR,    // Vector base + 0xC8   Reserved

  Unimplemented_ISR,    // Vector base + 0xCA   Reserved

  Unimplemented_ISR,    // Vector base + 0xCC   Port H

  Unimplemented_ISR,    // Vector base + 0xCE   Port J

  Unimplemented_ISR,    // Vector base + 0xD0   Reserved

  Unimplemented_ISR,    // Vector base + 0xD2   ATD0

  Unimplemented_ISR,    // Vector base + 0xD4   SCI1

  Unimplemented_ISR,    // Vector base + 0xD6   SCI0    

  Unimplemented_ISR,    // Vector base + 0xD8   SPI0    

  Unimplemented_ISR,    // Vector base + 0xDA   TIM Pulse accumulator input edge     

  Unimplemented_ISR,    // Vector base + 0xDC   TIM Pulse accumulator A overflow     

  Unimplemented_ISR,    // Vector base + 0xDE   TIM timer overflow     

  Unimplemented_ISR,    // Vector base + 0xE0   TIM timer channel 7     

  Unimplemented_ISR,    // Vector base + 0xE2   TIM timer channel 6     

  Unimplemented_ISR,    // Vector base + 0xE4   TIM timer channel 5     

  Unimplemented_ISR,    // Vector base + 0xE6   TIM timer channel 4     

  Unimplemented_ISR,    // Vector base + 0xE8   TIM timer channel 3     

  Unimplemented_ISR,    // Vector base + 0xEA   TIM timer channel 2     

  Unimplemented_ISR,    // Vector base + 0xEC   TIM timer channel 1     

  Unimplemented_ISR,    // Vector base + 0xEE   TIM timer channel 0     

   RTI_ISR,    // Vector base + 0xF0   Real time interrupt

  Unimplemented_ISR,    // Vector base + 0xF2   IRQ     

  Unimplemented_ISR,    // Vector base + 0xF4   XIRQ     

  Unimplemented_ISR,    // Vector base + 0xF6   SWI     

  Unimplemented_ISR     // Vector base + 0xF8   Unimplemented instruction trap     

};