[资源共享] （FPGA实验五）：Verilog HDL语言数码管时钟（时分秒）

bqgup 2019-4-26 19:49 楼主

Verilog HDL语言写得数码管时钟

module smg(
input ext_clk_50M,
inout reg div_clk_1K,
output reg[7:0]wei_xuan,
output reg[7:0]duan_xuan
);
reg [31:0]cnt;
reg [31:0]cnt1;//time
reg div_clk_1Hz;
reg [7:0]sec;
reg [7:0]min;
reg [7:0]h;
reg [2:0]duan_num;
always [url=home.php?mod=space&uid=775551]@[/url] (posedge ext_clk_50M)//scan clk
if(cnt == 32'd10_000)
begin
cnt <= 32'd0;
div_clk_1K <= ~div_clk_1K;
end
else cnt <= cnt + 32'd1;
always @ (posedge ext_clk_50M)//time clk
if(cnt1 == 32'd25_000_000)
begin
cnt1 <= 32'd0;
div_clk_1Hz <= ~div_clk_1Hz;
end
else cnt1 <= cnt1 + 32'd1;
////////////////////////////////////////////////////////////////
always @(posedge div_clk_1Hz)
if(sec == 8'd59)
begin
sec <= 8'd0;
min <= min + 8'd1;
if(min == 8'd59)
begin
min <= 8'd0;
h <= h + 8'd1;
if(h == 8'd23)
h <= 8'd0;
end
end
else sec <= sec + 8'd1;
////////////////////////////////////////////////////////////////
always @ (posedge div_clk_1K)
if(duan_num == 3'b110) duan_num <= 3'b0;
else duan_num <= duan_num + 3'b1;
always @ (sec or min or h or duan_num)//encoder
if(duan_num == 3'b001)
begin
wei_xuan <= 8'b0111_1111;
case(sec % 10)
8'd0: duan_xuan <= 8'b1100_0000;//0
8'd1: duan_xuan <= 8'b1111_1001;//1
8'd2: duan_xuan <= 8'b1010_0100;//2
8'd3: duan_xuan <= 8'b1011_0000;//3
8'd4: duan_xuan <= 8'b1001_1001;//4
8'd5: duan_xuan <= 8'b1001_0010;//5
8'd6: duan_xuan <= 8'b1000_0011;//6
8'd7: duan_xuan <= 8'b1111_1000;//7
8'd8: duan_xuan <= 8'b1000_0000;//8
8'd9: duan_xuan <= 8'b1001_0000;//9
endcase
end
else if(duan_num == 3'b010)
begin
wei_xuan <= 8'b1011_1111;
case(sec / 10)
8'd0: duan_xuan <= 8'b1100_0000;//0
8'd1: duan_xuan <= 8'b1111_1001;//1
8'd2: duan_xuan <= 8'b1010_0100;//2
8'd3: duan_xuan <= 8'b1011_0000;//3
8'd4: duan_xuan <= 8'b1001_1001;//4
8'd5: duan_xuan <= 8'b1001_0010;//5
8'd6: duan_xuan <= 8'b1000_0011;//6
8'd7: duan_xuan <= 8'b1111_1000;//7
8'd8: duan_xuan <= 8'b1000_0000;//8
8'd9: duan_xuan <= 8'b1001_0000;//9
endcase
end
else if(duan_num == 3'b011)
begin
wei_xuan <= 8'b1110_1111;
case(min % 10)
8'd0: duan_xuan <= 8'b1100_0000;//0
8'd1: duan_xuan <= 8'b1111_1001;//1
8'd2: duan_xuan <= 8'b1010_0100;//2
8'd3: duan_xuan <= 8'b1011_0000;//3
8'd4: duan_xuan <= 8'b1001_1001;//4
8'd5: duan_xuan <= 8'b1001_0010;//5
8'd6: duan_xuan <= 8'b1000_0011;//6
8'd7: duan_xuan <= 8'b1111_1000;//7
8'd8: duan_xuan <= 8'b1000_0000;//8
8'd9: duan_xuan <= 8'b1001_0000;//9
endcase
end
else if(duan_num == 3'b100)
begin
wei_xuan <= 8'b1111_0111;
case(min / 10)
8'd0: duan_xuan <= 8'b1100_0000;//0
8'd1: duan_xuan <= 8'b1111_1001;//1
8'd2: duan_xuan <= 8'b1010_0100;//2
8'd3: duan_xuan <= 8'b1011_0000;//3
8'd4: duan_xuan <= 8'b1001_1001;//4
8'd5: duan_xuan <= 8'b1001_0010;//5
8'd6: duan_xuan <= 8'b1000_0011;//6
8'd7: duan_xuan <= 8'b1111_1000;//7
8'd8: duan_xuan <= 8'b1000_0000;//8
8'd9: duan_xuan <= 8'b1001_0000;//9
endcase
end
else if(duan_num == 3'b101)//h
begin
wei_xuan <= 8'b1111_1101;
case(h % 10)
8'd0: duan_xuan <= 8'b1100_0000;//0
8'd1: duan_xuan <= 8'b1111_1001;//1
8'd2: duan_xuan <= 8'b1010_0100;//2
8'd3: duan_xuan <= 8'b1011_0000;//3
8'd4: duan_xuan <= 8'b1001_1001;//4
8'd5: duan_xuan <= 8'b1001_0010;//5
8'd6: duan_xuan <= 8'b1000_0011;//6
8'd7: duan_xuan <= 8'b1111_1000;//7
8'd8: duan_xuan <= 8'b1000_0000;//8
8'd9: duan_xuan <= 8'b1001_0000;//9
endcase
end
else if(duan_num == 3'b110)//h
begin
wei_xuan <= 8'b1111_1110;
case(h / 10)
8'd0: duan_xuan <= 8'b1100_0000;//0
8'd1: duan_xuan <= 8'b1111_1001;//1
8'd2: duan_xuan <= 8'b1010_0100;//2
8'd3: duan_xuan <= 8'b1011_0000;//3
8'd4: duan_xuan <= 8'b1001_1001;//4
8'd5: duan_xuan <= 8'b1001_0010;//5
8'd6: duan_xuan <= 8'b1000_0011;//6
8'd7: duan_xuan <= 8'b1111_1000;//7
8'd8: duan_xuan <= 8'b1000_0000;//8
8'd9: duan_xuan <= 8'b1001_0000;//9
endcase
end
endmodule

代码写完使用JTAG（联合测试行动组）下载观看效果：

HDL语言数码管时钟.mp4 (1.15 MB)
(下载次数: 11, 2019-4-26 19:37 上传)

数码管的效果是这样：

效果是这样的，看起来有点不太符合我们日常的观看习惯，我们对代码做个修改，让效果看起来更舒适。

module smg(
input ext_clk_50M,
inout reg div_clk_1K,
output reg[7:0]wei_xuan,
output reg[7:0]duan_xuan
);
reg [31:0]cnt;
reg [31:0]cnt1;//time
reg div_clk_1Hz;
reg [7:0]sec;
reg [7:0]min;
reg [7:0]h;
reg [3:0]duan_num;
always @ (posedge ext_clk_50M)//scan clk
if(cnt == 32'd10_000)
begin
cnt <= 32'd0;
div_clk_1K <= ~div_clk_1K;
end
else cnt <= cnt + 32'd1;
always @ (posedge ext_clk_50M)//time clk
if(cnt1 == 32'd25_000_000)
begin
cnt1 <= 32'd0;
div_clk_1Hz <= ~div_clk_1Hz;
end
else cnt1 <= cnt1 + 32'd1;
////////////////////////////////////////////////////////////////
always @(posedge div_clk_1Hz)
if(sec == 8'd59)
begin
sec <= 8'd0;
min <= min + 8'd1;
if(min == 8'd59)
begin
min <= 8'd0;
h <= h + 8'd1;
if(h == 8'd23)
h <= 8'd0;
end
end
else sec <= sec + 8'd1;
////////////////////////////////////////////////////////////////
always @ (posedge div_clk_1K)
if(duan_num == 4'b1000) duan_num <= 4'b0;
else duan_num <= duan_num + 4'b1;
always @ (sec or min or h or duan_num)//encoder
if(duan_num == 4'b0001)
begin
wei_xuan <= 8'b0111_1111;
case(sec % 10)
8'd0: duan_xuan <= 8'b1100_0000;//0
8'd1: duan_xuan <= 8'b1111_1001;//1
8'd2: duan_xuan <= 8'b1010_0100;//2
8'd3: duan_xuan <= 8'b1011_0000;//3
8'd4: duan_xuan <= 8'b1001_1001;//4
8'd5: duan_xuan <= 8'b1001_0010;//5
8'd6: duan_xuan <= 8'b1000_0011;//6
8'd7: duan_xuan <= 8'b1111_1000;//7
8'd8: duan_xuan <= 8'b1000_0000;//8
8'd9: duan_xuan <= 8'b1001_0000;//9
endcase
end
else if(duan_num == 4'b0010)
begin
wei_xuan <= 8'b1011_1111;
case(sec / 10)
8'd0: duan_xuan <= 8'b1100_0000;//0
8'd1: duan_xuan <= 8'b1111_1001;//1
8'd2: duan_xuan <= 8'b1010_0100;//2
8'd3: duan_xuan <= 8'b1011_0000;//3
8'd4: duan_xuan <= 8'b1001_1001;//4
8'd5: duan_xuan <= 8'b1001_0010;//5
8'd6: duan_xuan <= 8'b1000_0011;//6
8'd7: duan_xuan <= 8'b1111_1000;//7
8'd8: duan_xuan <= 8'b1000_0000;//8
8'd9: duan_xuan <= 8'b1001_0000;//9
endcase
end
else if(duan_num == 4'b0011)
begin
wei_xuan <= 8'b1110_1111;
case(min % 10)
8'd0: duan_xuan <= 8'b1100_0000;//0
8'd1: duan_xuan <= 8'b1111_1001;//1
8'd2: duan_xuan <= 8'b1010_0100;//2
8'd3: duan_xuan <= 8'b1011_0000;//3
8'd4: duan_xuan <= 8'b1001_1001;//4
8'd5: duan_xuan <= 8'b1001_0010;//5
8'd6: duan_xuan <= 8'b1000_0011;//6
8'd7: duan_xuan <= 8'b1111_1000;//7
8'd8: duan_xuan <= 8'b1000_0000;//8
8'd9: duan_xuan <= 8'b1001_0000;//9
endcase
end
else if(duan_num == 4'b0100)
begin
wei_xuan <= 8'b1111_0111;
case(min / 10)
8'd0: duan_xuan <= 8'b1100_0000;//0
8'd1: duan_xuan <= 8'b1111_1001;//1
8'd2: duan_xuan <= 8'b1010_0100;//2
8'd3: duan_xuan <= 8'b1011_0000;//3
8'd4: duan_xuan <= 8'b1001_1001;//4
8'd5: duan_xuan <= 8'b1001_0010;//5
8'd6: duan_xuan <= 8'b1000_0011;//6
8'd7: duan_xuan <= 8'b1111_1000;//7
8'd8: duan_xuan <= 8'b1000_0000;//8
8'd9: duan_xuan <= 8'b1001_0000;//9
endcase
end
else if(duan_num == 4'b0101)//h
begin
wei_xuan <= 8'b1111_1101;
case(h % 10)
8'd0: duan_xuan <= 8'b1100_0000;//0
8'd1: duan_xuan <= 8'b1111_1001;//1
8'd2: duan_xuan <= 8'b1010_0100;//2
8'd3: duan_xuan <= 8'b1011_0000;//3
8'd4: duan_xuan <= 8'b1001_1001;//4
8'd5: duan_xuan <= 8'b1001_0010;//5
8'd6: duan_xuan <= 8'b1000_0011;//6
8'd7: duan_xuan <= 8'b1111_1000;//7
8'd8: duan_xuan <= 8'b1000_0000;//8
8'd9: duan_xuan <= 8'b1001_0000;//9
endcase
end
else if(duan_num == 4'b0110)//h
begin
wei_xuan <= 8'b1111_1110;
case(h / 10)
8'd0: duan_xuan <= 8'b1100_0000;//0
8'd1: duan_xuan <= 8'b1111_1001;//1
8'd2: duan_xuan <= 8'b1010_0100;//2
8'd3: duan_xuan <= 8'b1011_0000;//3
8'd4: duan_xuan <= 8'b1001_1001;//4
8'd5: duan_xuan <= 8'b1001_0010;//5
8'd6: duan_xuan <= 8'b1000_0011;//6
8'd7: duan_xuan <= 8'b1111_1000;//7
8'd8: duan_xuan <= 8'b1000_0000;//8
8'd9: duan_xuan <= 8'b1001_0000;//9
endcase
end
else if(duan_num == 4'b0111)//-
begin
wei_xuan <= 8'b1111_1011;
duan_xuan <= 8'b1011_1111;//-
end
else if(duan_num == 4'b1000)//-
begin
wei_xuan <= 8'b1101_1111;
duan_xuan <= 8'b1011_1111;//-
end
endmodule

修改完的效果如下所示，个人感觉看出来比较舒服：

8位数码管.mp4 (1.16 MB)
(下载次数: 9, 2019-4-26 19:46 上传)

最后分享一下工程，方便大家使用下载：

4.4、数码管动态显示（时分秒）.rar (1.15 MB)
(下载次数: 35, 2019-4-26 19:48 上传)

4.5、数码管动态显示（时分秒8段）.rar (1.17 MB)
(下载次数: 68, 2019-4-26 19:48 上传)

欢迎大家讨论交流。 本帖最后由 bqgup 于 2019-4-26 19:51 编辑

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