请教一个verilog 程序！

lingfeng 2009-6-25 14:51 楼主

前仿没有问题，用Quater 2编译也成功了，但后仿时出现网表文件错误……

请高人指教……

谢谢……
`timescale 1ns/100ps
`define clk_cycle 50

module sim_all(clk,rst,rst1,wr_en,rd_en);

input clk,rst,rst1,wr_en,rd_en;
wire [7:0]d_out;
wire clk_10mb;
wire clk_out;
wire[7:0] addr,out,wr_addr;
reg[7:0] data;

   fdivision  a(.clk(clk),.clk_10mb(clk_10mb));
   half_clk  b(.clk_in(clk_10mb),.clk_out(clk_out));
   dram    c(.clk(clk_10mb),.rst(rst),.wr_en(wr_en),.rd_en(rd_en),.wr_addr(addr),.d_out(d_out));
   counter  d(.out(out),.data(d_out),.clk_5mb(clk_out),.rst(rst1),.en(rd_en));
   addr_generator f(.rst(rst),.clk(clk_10mb),.enable(wr_en),.addr(addr));
endmodule

module fdivision(clk,clk_10mb);
input clk;
output clk_10mb;
reg clk_10mb=0;
reg[7:0] j=8'd0;
always@(posedge clk )
begin
      if(j==4)
      begin
         j<=0;
         clk_10mb<=~clk_10mb;
      end
      else
      j<=j+8'd1;
end
endmodule

module half_clk(clk_in,clk_out);
input clk_in;
output clk_out;
reg clk_out=0;
   always@(posedge clk_in)
begin
clk_out<=~clk_out ;
end
endmodule

module dram(clk,rst,wr_en,rd_en,d_out,wr_addr);
input clk,rst,wr_en,rd_en;
input[7:0]wr_addr;

output[7:0] d_out;
reg[7:0] d_out;
reg[7:0] memory[0:255];
reg[7:0] rd_addr;

always @(posedge clk or negedge rst)
begin
  if(!rst )
  begin
rd_addr<=wr_addr;
memory[wr_addr]<=wr_addr;
  end
end

always @(posedge clk)
begin
  if(rd_en)
  d_out<=memory[rd_addr];
end
endmodule

module counter(out,data,clk_5mb,rst,en);
input [7:0] data;
input clk_5mb,rst,en;
output[7:0] out;
reg[7:0] out;

always@(posedge clk_5mb )

begin
if(!rst)
      else if(en)
   out<=out+8'd1;
      end
endmodule

module addr_generator(rst,clk,enable,addr);
input rst,clk,enable;
output[7:0] addr;
reg[7:0] addr;
always@(posedge rst or posedge clk )
begin
  if(rst)
addr=8'h0;
  else if(enable)
addr<=addr+8'd1;
end
endmodule

激励：

`timescale 1ns/100ps
`define clk_cycle 50
module sim_all_tb;
reg clk,rst,rst1,wr_en,rd_en;
reg [7:0] data_in;
reg [7:0] data_out;
reg [7:0] wr_addr;
reg [7:0] rd_addr;
wire rest,clk_in,clk_out,clk_10mb,clk_5mb;

wire[7:0] d_out,d_in,data,out;

always #`clk_cycle clk=~clk;
sim_all uut(.clk(clk),.rst(rst),.rst1(rst1),.wr_en(wr_en),.rd_en(rd_en));
initial
begin
      clk=0;rst=1;wr_en=0;rd_en=0;rst1=1;
end
initial
begin
   #1000 rst=1;
   #1000 rst=0;
   #1000 rd_en=1;
   #1000 rst1=0;
   #2000 rst1=1;
   #1000 wr_en=1;
   #1000 wr_en=0;
   #1000 rst1=0;
   #2000 rst1=1;
   #3000 wr_en=1;
   #1000 wr_en=0;
   #1000 rst1=0;
   #2000 rst1=1;
   #100000 $stop;
end
endmodule

本文来自eeworld博客，转载请标明出处：http://blog.eeworld.net/zoupgfj/archive/2009/06/25/4297691.aspx