Reset operation
As discussed previously, CE# must be low for all NAND activities. The simplest NAND command is the Reset (FFh), which doesn't require any address or second cycle. Simply assert CLE and issue a write pulse with FFh on the data bus, and a Reset operation is performed. Reset is one of two commands that can be issued while the NAND device is busy. If it's busy processing a previous command, issuing a Reset aborts the previous operation. Note that if the previous operation was an Erase or Program command, issuing a Reset aborts the command prematurely, and the desired operation doesn't complete. Because Erase and Program can be time-consuming operations, they can be aborted with a Reset and re-issued later.
Read ID operation
The Read ID (90h) command requires one dummy address cycle (00h), but doesn't need a second command cycle (Table 1, again). After issuing the command and dummy address, the ID data can be read out by keeping CLE and ALE low and toggling the RE# signal for each byte of ID.
Read status operation
Read Status (70h) is the second command that can be issued while the NAND device is busy. This command doesn't require an address or second command cycle. The NAND device's status can be interrogated by issuing the RE# clock signal. If the Read Status command is used to monitor the device's ready state, the command should only be issued one time and the status re-read by re-issuing the RE# clock. Alternatively, the RE# signal can be kept low waiting for the appropriate status bit. Read Status also includes the status of the write protect pin as well as the pass/fail status of the previous Program or Erase operations. It's mandatory that successful status be attained on Program or Erase operations to ensure proper data integrity.
The Block Erase (60h) operation erases an entire block of 64 pages or 128 bytes total. To issue this operation, use the WE# signal to clock in the Erase command (60h) with CLE asserted. Next, clock in three address cycles, keeping ALE asserted for each address byte. The three address cycles are the most significant address cycles of Table 2, which includes the block and page addresses. The page address portion (the low order 6 bits of the third address cycle) is ignored, and only the block address portion of the three most significant bytes is used. Once the address is input completely, issue the second command (command cycle 2) of D0h, which also gets clocked in with WE# while CLE is being asserted. This confirms the erase operation, and the device goes busy for roughly 2 ms. When this operation completes, the device is ready for another command. Notice the Read Status command can be issued at any time, even when the device is busy during the erase. The processor or controller could interrogate the device using the read status command.
Program operations
Program operations can only program bits to 0, and assume that you started with a previously-erased block. If you don't want to program a bit, keep it in its erased state by setting that particular bit (or group of bits) to 1. When the Program Page (80h) command is received, the input register is reset to all 1s (internally). This lets the user input only data bytes that he wants to program with 0 bits. The Program operation starts with the 80h command, with CLE asserted (Fig. 4). Next, drop CLE and assert ALE to input the full five address cycles.
Click here for Fig. 4
4. When the Program Page (80h) command is received, the input register is internally reset to all 1s, letting the user input only data bytes that he wants to program with 0 bits.
After the command and address are input, data is input to the register. Once all the data has been input, we issue the confirm command (10h) and start the programming operation. A Program operation typically requires 300 μs, although it may require up to 700 μs. It's mandatory that you read the status and check for successful operation. If the operation isn't successful, log the block and don't use it in the future. Move all data from the block to a good block.
Random data input operation
The next command is the random data input command (85h). This command only requires two bytes of address followed by the data (Fig. 5). It's useful when you want to jump around within a page, to access ECC data, for example. Random data input can be used to jump to the end of the page and write the ECC data. You can input as many address and data combinations as needed. It's only when the program confirm command (10h) is issued that the data is actually programmed to the selected page.
Click here for Fig. 5
5. Show is the Program command with random data input. The highlighted section shows that this command only requires two bytes of address followed by the data.
Due to the NAND page's large size, partial page programming is needed to store smaller-sized data. Each NAND page could accommodate four PC-sized 512-byte sectors. The spare area of each page provides additional storage for ECC and other information. While it's advantageous to write all four sectors at once, it's not always possible. An example of this is when you are appending a file. The file might start out as 512 bytes, with additional data coming later, making it 1024 bytes. In this case, writing the second 512 bytes would require a second page program operation to the NAND device. The maximum specification for partial page programming is eight; this would accommodate four data sectors and ECC, each programmed separately.
There are two common methods for storing data and spare information in the same page (Fig. 6). The first contains a data area of 512 bytes with the spare area directly adjacent to it. The spare area in this case is 16 bytes. Therefore, a 2112-byte page could contain four 528-byte elements. The second implementation involves storing the data and spare information separately. This means the 512-byte data is stored first, and the respective spare information for that data is stored at the end of the array starting at the beginning of the spare area. The second 512 bytes is stored next to the first 512, and the associated spare area for the second 512 is stored in the next 16-byte spare area. This continues until all four 512-byte sectors are stored with their respective 16-byte spare areas.
Read operation
A read operation starts with a command (00h), followed by five address cycles, followed by the read confirm (30h). After the read transfer time (tR) of approximately 25 μs, the data is loaded into the register and ready for output. Issuing the read enable (RE#) clock lets the NAND output the first byte corresponding to the column address specified in the address. Subsequent RE# transitions output successive locations. When RE# is high (not asserted), the I/O lines are tri-stated. Also, reading past the end of the device (byte 2112 or word 1056) results in reading invalid data. Random data can be directly accessed by issuing the (05h) command, two address cycles, and a (E0h) confirmation cycle. Once the page has been read from the array, this command provides rapid access to the data.
The NAND device actually has two registers: a data register and a cache register (Fig. 7). The Page read cache mode command lets you pipeline the next sequential access from the array while outputting the previously-accessed data. This double-buffered technique allows you to hide the read access time (tR). Data is first transferred from the NAND array to the data register. If the cache register is available (not busy), the data is quickly moved from the data register to the cache register. Once it's been transferred to the cache register, the data register is available and can start to load the next sequential page from the NAND array.
7. Shown is the page read cache mode.
A 33% performance improvement can be achieved on an 8-bit I/O device, resulting in up to 31 Mbytes/s of throughput. With the16-bit I/O device, throughput can be increased to 37 Mbytes/s, a 40% improvement over the normal Page read operation. Read cache can be especially useful during system boot-up, when large amounts of data are typically read from NAND and start-up time is critical.
Program page cache mode command
Program page cache mode provides performance improvement over normal Program page operations. This double-buffered technique lets the controller input data directly to the cache register and uses the data register as a holding register to supply the programming of the array. This frees the cache register so that the next sequential page operation can be loaded in parallel. In many applications, the programming time (tPROG) can be completely hidden. Like the page read cache mode command, the data register maintains the data through the entire programming cycle. This frees up the cache register so that it can start receiving the next page of data from the controller.
Read for internal data move (00h, 35h), or copy back, is another useful system-level command. It provides the ability to move data from one page to another internally without leaving the NAND device. The Read for internal data move operation transfers the data read from the NAND array to the cache register. It can then be programmed into another page of the NAND device. This is beneficial in cases where the controller needs to move data out of a block before erasing that block. It's also possible to modify the data read before the program operation starts. This could be useful if you wanted to change the data before programming. This feature allows data to be moved around within the NAND device without tying up the processor or the I/O bus.
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