这段VHDL代码实现了什么功能啊

entity test is
  port(A,B:in bit_vector(3 downto 0);
  ALTB_N,AEQB_N,AGTB_N:out bit;
end COMP;
architecture com of test is
signal temp:bit_vector(1 downto 0);
begin
process(A,B)
   begin
   temp<="00";
   if A>B then temp<='1';
     else if A      end if;
    end process;
(ALTB_N,AGTB_N)<=temp;
AEQB_N<=not(temp(1)or temp(0));
end com;


本人刚接触VHDL，望指教