由FPGA 做的电子钟，可是输出全为0（六位），希望大家帮忙看一下

mcd511786450 2007-11-28 19:57 楼主

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clock IS
PORT(
  CLK : IN STD_LOGIC;
  REST: IN STD_LOGIC;//复位键
  MIN : IN STD_LOGIC;//分位加一键
  HOUR: IN STD_LOGIC;//时位加一键
  SEGOUT: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);//输出
  SELOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));//数码管位的选择
END ENTITY;
ARCHITECTURE STRUCT OF clock IS
SIGNAL NUM: INTEGER RANGE 0 TO 5;//定义变量，由NUM选择数字
SIGNAL SEG: STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL SEL: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CLK1: STD_LOGIC;
SIGNAL S: INTEGER RANGE 0 TO 5;
SIGNAL FULL:STD_LOGIC;
SIGNAL MIN1:STD_LOGIC;
SIGNAL HOUR1:STD_LOGIC;
SIGNAL REST1:STD_LOGIC;
BEGIN
MIN1 <=MIN;//将MIN付给MIN;
HOUR1 <= HOUR;//将HOUR付给HOUR1;
REST1 <=REST;//将REST付给REST1;
P1:PROCESS(CLK)
  VARIABLE Q: INTEGER RANGE 0 TO 60000;//12M分频；
BEGIN
  IF CLK'EVENT AND CLK = '1' THEN
Q := Q + 1;
IF Q <=  29999 THEN
clk1 <= '0';
ELSIF Q > 2999 AND Q <= 60000 THEN
clk1 <= '1';
ELSE
Q := 0;
END IF;
  END IF;
END PROCESS;
P3:PROCESS(CLK1,S)//对数码管进行扫描
BEGIN
IF CLK1 'EVENT AND CLK1 = '1' THEN
  IF S <= 7 THEN
   S <= S + 1;
  ELSE
   S <= 0;
  END IF;
  END IF;
END PROCESS;
P4:PROCESS(CLK1,S,MIN,HOUR)
variable DBS0: INTEGER RANGE 0 TO 9;//控制秒个位
variable DBS1: INTEGER RANGE 0 TO 5;//控制秒十位
variable DBM0: INTEGER RANGE 0 TO 9;//控制分个位
VARIABLE DBM1: INTEGER RANGE 0 TO 5;//控制分十位
VARIABLE DBH0: INTEGER RANGE 0 TO 9;//控制时个位
VARIABLE DBH1: INTEGER RANGE 0 TO 2;//控制时十位
VARIABLE count1: INTEGER RANGE 0 TO 200;//将COUNT1付为200
BEGIN
   IF CLK1 'EVENT AND CLK1= '1' THEN
      count1 := count1 + 1;
      IF COUNT1 = 200 THEN
         COUNT1 := 0;//COUNT1满200后付值为0，将频率分为1HZ
      IF  DBS0 = 9 THEN
         DBS0 := 0;
         DBS0 := DBS0 + 1;

      IF DBS1 = 5 THEN
         DBS1 := 0;
         DBS1 := DBS1 + 1;

      IF DBM0 = 9 THEN
         DBM0 := 0；
         DBM0 := DBM0 + 1;

      IF DBM1 = 5 THEN
         DBM1 := 0;
         DBM1 := DBM1 + 1;

      IF DBH0 =4 AND DBH1=2  THEN
         DBH0 := 0;
      ELSIF DBH0 =9 THEN
            DBH0 :=DBH0 + 1;

      IF DBH1 = 2 THEN
         DBH1 := 0;
         DBH1 := DBH1+1;
      END IF;
      END IF;
      END IF;
      END IF;
      END IF;
      END IF;
IF REST1 'EVENT AND REST1 ='1' THEN//当REST有上升延时，全部数码管全部未零；
      DBS0 := 0;
      DBS1 := 0;
      DBM0 := 0;
      DBM1 := 0;
      DBH0 := 0;
      DBH1 := 0;
      END IF;
   IF MIN1 'EVENT AND MIN1='1' THEN
      DBS0:=DBS0+1;
   END IF;
   IF HOUR1 'EVENT AND HOUR1='1' THEN
      DBH0:=DBH0+1;
      END IF;
END IF;
CASE S IS    //对 S进行判别
   WHEN 0 => SEL <= "00000001";NUM <= DBS0;//秒个位的选通码
   WHEN 1 => SEL <= "00000010";NUM <= DBS1;
   WHEN 2 => SEL <= "00000100";NUM <= DBM0;
   WHEN 3 => SEL <= "00001000";NUM <= DBM1;
   WHEN 4 => SEL <= "00010000";NUM <= DBH0;
   WHEN 5 => SEL <= "00100000";NUM <= DBH1;
  END CASE;
END IF;
END PROCESS;
P5:PROCESS(CLK1,NUM)
BEGIN
IF CLK1 'EVENT AND CLK1= '1' THEN
CASE NUM IS
   WHEN  0 => SEG <= "0000001";//0的编码
   WHEN  1 => SEG <= "0000001";
   WHEN  2 =>SEG <= "0010010" ;
   WHEN  3 =>SEG <= "0000110";
   WHEN  4 => SEG <= "1001100";
   WHEN  5 =>SEG <= "0100100" ;
   WHEN  6 =>SEG <= "0100000" ;
   WHEN  7 =>SEG <= "0001111";
   WHEN  8 => SEG <= "0000000";
   WHEN  9 =>SEG <= "0000100" ;
   WHEN OTHERS =>NULL;
END CASE;
END IF;
END PROCESS;
P6:PROCESS(SEG,SEL)BEGIN//将选通信号，数码馆的编码发出
SELOUT <= SEL;
SEGOUT(6 DOWNTO 0) <= SEG;
END PROCESS;
END ARCHITECTURE STRUCT;