单片机的系列比较---M0与M3

Cortex-M3和Cortex-M0的区别

ARM架构自v6开始分为A/R/M三个系列。CM0/CM3都是属于M系列的。CortexM0是基于v6架构；CortexM3是v7架构。

主要区别
性能：
Cortex-M0 基于32 位架构，利用一个
通过MULS 指令直接与内核相连的32×32 位硬件乘
法器，恩智浦M0 指令模式可以在单个周期中对两个
32 位字进行乘运算.
最高频率50MHZ-

Cortex-M3处理器的核心是基于哈佛架构的3级流水线内核，
该内核集成了分支预测，单周期乘法，
硬件除法等众多功能强大的特性
最高频率已经达到150MHZ+

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另附上英文手册数据比较：

Cortex-M0
Architecture        ARMv6-M (Von Neumann)
ISA support        Thumb®/ Thumb-2 technology*
Pipeline        3-stage
Dhrystone        0.9 DMIPS/MHz
Interrupts        NMI + 1 to 32 physical interrupts
Interrupt latency        16 cycles
Sleep modes        Integrated WFI and WFE instructions
Sleep & Deep Sleep Signals
Optional Retention Mode with Power Management Kit
Enhanced Instructions        Single-cycle (32x32) multiply
Debug        JTAG or Serial-Wire Debug ports

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Cortex-M3 Features
Architecture        ARMv7-M (Harvard)
ISA Support        Thumb® / Thumb-2
Pipeline        3-stage + branch speculation
Dhrystone        1.25 DMIPS/MHz
Memory Protection        Optional 8 region MPU with sub regions and background region
Interrupts        Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Latency        12 cycles
Inter-Interrupt Latency        6 cycles
Interrupt Priority Levels        8 to 256 priority levels
Wake-up Interrupt Controller        Up to 240 Wake-up Interrupts
Sleep Modes       
Integrated WFI and WFE Instructions and Sleep On Exit capability.

Sleep & Deep Sleep Signals.

Optional Retention Mode with ARM Power Management Kit

Bit Manipulation        Integrated Instructions & Bit Banding
Enhanced Instructions        Hardware Divide (2-12 Cycles) & Single-Cycle (32x32) Multiply.
Debug        Optional JTAG & Serial-Wire Debug Ports. Up to 8 Breakpoints and 4 Watchpoints.