请问USI的I2C怎么用?

toor 2011-10-15 11:10 楼主

芯片资料上的USI寄存器有点看不明白, 硬件上是不是集成了SPI,I2C的收发器还是要软件模拟? 从TI官网上下了个USI_I2CMaster的函数库,初始化的时候端口上看不到波形,USI_I2CSelect E2PROM的就死在里面了,应该是等不到响应信号.

不知道哪里有更详细的资料说明? 谢谢!

回复评论（4）

沙发 wl1336412

群共享上有例程的
硬件上集成了I2C，设置相应寄存器就成了，有啥不明白的？

14.2.4.1 I2C Master Mode
To configure the USI module as an I2C master the USIMST bit must be set. In master mode, clocks are
generated by the USI module and output to the SCL line while USIIFG = 0. When USIIFG = 1, the SCL
will stop at the idle, or high, level. Multi-master operation is supported as described in the Arbitration
section.
The master supports slaves that are holding the SCL line low only when USIDIVx > 0. When USIDIVx is
set to /1 clock division (USIDIVx = 0), connected slaves must not hold the SCL line low during data
transmission. Otherwise the communication may fail.
14.2.4.2 I2C Slave Mode
To configure the USI module as an I2C slave the USIMST bit must be cleared. In slave mode, SCL is held
low if USIIFG = 1, USISTTIFG = 1 or if USICNTx = 0. USISTTIFG must be cleared by software after the
slave is setup and ready to receive the slave address from a master.
14.2.4.3 I2C Transmitter
In transmitter mode, data is first loaded into USISRL. The output is enabled by setting USIOE and the
transmission is started by writing 8 into USICNTx. This clears USIIFG and SCL is generated in master
mode or released from being held low in slave mode. After the transmission of all 8 bits, USIIFG is set,
and the clock signal on SCL is stopped in master mode or held low at the next low phase in slave mode.
To receive the I2C acknowledgment bit, the USIOE bit is cleared with software and USICNTx is loaded
with 1. This clears USIIFG and one bit is received into USISRL. When USIIFG becomes set again, the
LSB of USISRL is the received acknowledge bit and can be tested in software.