17.4.12 IFG2, Interrupt Flag Register 2 ................................. 484
17.4.13 UC1IE, USCI_B1 Interrupt Enable Register ........................................ 484
17.4.14 UC1IFG, USCI_B1 Interrupt Flag Register ......................................... 485
18
USART Peripheral Interface, UART Mode
异步串行通信接口，异步模式 ................................ 487
18.1
USART Introduction: UART Mode ......................................... 488
18.2
USART Operation: UART Mode ........................................... 489
18.2.1 USART Initialization and Reset .................................. 489
18.2.2 Character Format .................................................. 490
18.2.3 Asynchronous Communication Formats .. 异步通信格式 ..异步的 . 490
18.2.4 USART Receive Enable .......................................... 493
18.2.5 USART Transmit Enable .......................................... 493
18.2.6 USART Baud Rate Generation .................................. 494
18.2.7 USART Interrupts .................................................. 500
18.3
USART Registers: UART Mode ............................................ 503
18.3.1 UxCTL, USART Control Register ................................ 504
18.3.2 UxTCTL, USART Transmit Control Register ......................................... 505
18.3.3 UxRCTL, USART Receive Control Register ......................................... 506
18.3.4 UxBR0, USART Baud Rate Control Register 0 ...................................... 506
18.3.5 UxBR1, USART Baud Rate Control Register 1 ...................................... 506
18.3.6 UxMCTL, USART Modulation Control Register 调制 控制寄存器 507
18.3.7 UxRXBUF, USART Receive Buffer Register ......................................... 507
18.3.8 UxTXBUF, USART Transmit Buffer Register ........................................ 507
18.3.9 ME1, Module Enable Register 1 ............. ..模块使能寄存器 ........... 507
18.3.10 ME2, Module Enable Register 2 ................................ 507
18.3.11 IE1, Interrupt Enable Register 1 ....................中断使能寄 ............ 508
18.3.12 IE2, Interrupt Enable Register 2 ............ ......... 508
18.3.13 IFG1, Interrupt Flag Register 1 .... ...中断 标志 寄存器 ............. 508
18.3.14 IFG2, Interrupt Flag Register 2 ................................. 509
19
USART Peripheral Interface, SPI Mode ................................... 511
19.1
USART Introduction: SPI Mode ............................................ 512
19.2
USART Operation: SPI Mode .............................................. 513
19.2.1 USART Initialization and Reset .................................. 513
19.2.2 Master Mode ........................................................ 514
19.2.3 Slave Mode ......................................................... 514
19.2.4 SPI Enable .......................................................... 515
19.2.5 Serial Clock Control ............................................... 516
19.2.6 SPI Interrupts ....................................................... 518
19.3
USART Registers: SPI Mode ............................................... 520
19.3.1 UxCTL, USART Control Register ................................ 521
19.3.2 UxTCTL, USART Transmit Control Register ......................................... 521
19.3.3 UxRCTL, USART Receive Control Register ......................................... 522
19.3.4 UxBR0, USART Baud Rate Control Register 0 ...................................... 522
19.3.5 UxBR1, USART Baud Rate Control Register 1 ...................................... 522
19.3.6 UxMCTL, USART Modulation Control Register ...................................... 522
19.3.7 UxRXBUF, USART Receive Buffer Register ......................................... 522
19.3.8 UxTXBUF, USART Transmit Buffer Register ........................................ 523
19.3.9 ME1, Module Enable Register 1 ................................. 523
19.3.10 ME2, Module Enable Register 2 ................................ 523
19.3.11 IE1, Interrupt Enable Register 1 ................................ 523
19.3.12 IE2, Interrupt Enable Register 2 ................................ 524
19.3.13 IFG1, Interrupt Flag Register 1 ................................. 524
19.3.14 IFG2, Interrupt Flag Register 2 ................................. 52
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