module time_m(clk,set,suspend,stop,clear,led,fen1,fen2,miao1,miao2,fenmiao1,fenmiao2);
parameter state0 = 2'b00,state1 = 2'b01,state2 = 2'b10,state3 = 2'b11;
input clk,set,suspend,stop,clear;
output[17:0]led;
output[6:0]fen1,fen2,miao1,miao2,fenmiao1,fenmiao2;
reg[6:0]fen1=0,fen2=0,miao1=0,miao2=0,fenmiao1=0,fenmiao2=0;
reg[17:0]led=0;
reg[4:0]flag=0;
reg flag1=0;
reg[5:0] cnt1 = 0;
reg[11:0] cnt2=0;
reg clk100hz=0;
reg clk10kz=0;
reg[5:0] min=0,sec=0;
reg[3:0]min1=0,min2=0,sec1=0,sec2=0,shifenmiao1=0,shifenmiao2=0;
reg[6:0]shifenmiao=0;
reg[1:0]state=0;
always @(posedge clk)
begin
if(cnt2 == 12'd2499)
begin
cnt2 <= 0;
clk10kz <= ~clk10kz;
end
else
cnt2 <= cnt2+1;
end
always @(posedge clk10kz)
begin
if(cnt1 == 6'd49)
begin
cnt1 <= 0;
clk100hz <= ~clk100hz;
end
else
cnt1 <= cnt1+1;
end
always @(negedge set or negedge suspend or negedge stop or negedge clear)
begin
if(!set)
state <= state0;
if(!suspend)
state <= state1;
if(!stop)
state <= state2;
if(!clear)
state <= state3;
end
always @(posedge clk100hz)
begin
case (state)
state0:
begin
if(flag1 == 1)
begin
shifenmiao <= 0;
sec <= 0;
min <= 0;
flag1 <= 0;
end
else
shifenmiao <= shifenmiao+1;
if(shifenmiao == 7'd99)
begin
shifenmiao <= 0;
sec <= sec + 1;
end
if(sec == 6'd59)
begin
sec <= 0;
min <= min + 1;
end
if(min == 6'd59)
begin
min <= 0;
end
end
state1:
begin
min <= min;
sec <= sec;
shifenmiao <= shifenmiao;
end
state2:
begin
min <= min;
sec <= sec;
shifenmiao <= shifenmiao;
flag1 <= 1;
end
state3:
begin
min <= 0;
sec <=0;
shifenmiao <=0;
end
default:
begin
min <= 0;
sec <= 0;
shifenmiao <= 0;
end
endcase
end
always @(min or sec or shifenmiao)
begin
min1 <= min/10;
min2 <= min%10;
sec1 <= sec/10;
sec2 <= sec%10;
shifenmiao1 <= shifenmiao/10;
shifenmiao2 <= shifenmiao%10;
end
always @(posedge clk100hz)
begin
case(state)
state0:
begin
if(!flag1)
if(flag == 18)
flag <= 0;
else
flag <= flag+1;
else flag <= 0;
end
state1:flag <= flag;
state2:flag <= flag;
state3:flag <= 0;
default: flag <= 0;
endcase
end
always @(flag)
begin
case(flag)
5'b00000:led = 18'b000000000000000000;
5'b00001:led = 18'b000000000000000001;
5'b00010:led = 18'b000000000000000010;
5'b00011:led = 18'b000000000000000100;
5'b00100:led = 18'b000000000000001000;
5'b00101:led = 18'b000000000000010000;
5'b00110:led = 18'b000000000000100000;
5'b00111:led = 18'b000000000001000000;
5'b01000:led = 18'b000000000010000000;
5'b01001:led = 18'b000000000100000000;
5'b01010:led = 18'b000000001000000000;
5'b01011:led = 18'b000000010000000000;
5'b01100:led = 18'b000000100000000000;
5'b01101:led = 18'b000001000000000000;
5'b01110:led = 18'b000010000000000000;
5'b01111:led = 18'b000100000000000000;
5'b10000:led = 18'b001000000000000000;
5'b10001:led = 18'b010000000000000000;
5'b10010:led = 18'b100000000000000000;
default: led = 18'b000000000000000000;
endcase
end
always @(posedge clk10kz)
begin
case(min1)
4'b0000:fen1<=7'b1000000;
4'b0001:fen1<=7'b1111001;
4'b0010:fen1<=7'b0100100;
4'b0011:fen1<=7'b0110000;
4'b0100:fen1<=7'b0011001;
4'b0101:fen1<=7'b0010010;
default:fen1<=7'b1111111;
endcase
case(min2)
4'b0000:fen2<=7'b1000000;
4'b0001:fen2<=7'b1111001;
4'b0010:fen2<=7'b0100100;
4'b0011:fen2<=7'b0110000;
4'b0100:fen2<=7'b0011001;
4'b0101:fen2<=7'b0010010;
4'b0110:fen2<=7'b0000010;
4'b0111:fen2<=7'b1111000;
4'b1000:fen2<=7'b0000000;
4'b1001:fen2<=7'b0010000;
default:fen2<=7'b1111111;
endcase
case(sec1)
4'b0000:miao1<=7'b1000000;
4'b0001:miao1<=7'b1111001;
4'b0010:miao1<=7'b0100100;
4'b0011:miao1<=7'b0110000;
4'b0100:miao1<=7'b0011001;
4'b0101:miao1<=7'b0010010;
default:miao1<=7'b1111111;
endcase
case(sec2)
4'b0000:miao2<=7'b1000000;
4'b0001:miao2<=7'b1111001;
4'b0010:miao2<=7'b0100100;
4'b0011:miao2<=7'b0110000;
4'b0100:miao2<=7'b0011001;
4'b0101:miao2<=7'b0010010;
4'b0110:miao2<=7'b0000010;
4'b0111:miao2<=7'b1111000;
4'b1000:miao2<=7'b0000000;
4'b1001:miao2<=7'b0010000;
default:miao2<=7'b1111111;
endcase
case(shifenmiao1)
4'b0000:fenmiao1<=7'b1000000;
4'b0001:fenmiao1<=7'b1111001;
4'b0010:fenmiao1<=7'b0100100;
4'b0011:fenmiao1<=7'b0110000;
4'b0100:fenmiao1<=7'b0011001;
4'b0101:fenmiao1<=7'b0010010;
4'b0110:fenmiao1<=7'b0000010;
4'b0111:fenmiao1<=7'b1111000;
4'b1000:fenmiao1<=7'b0000000;
4'b1001:fenmiao1<=7'b0010000;
default: fenmiao1<=7'b1111111;
endcase
case(shifenmiao1)
4'b000:fenmiao2<=7'b1000000;
4'b0001:fenmiao2<=7'b1111001;
4'b0010:fenmiao2<=7'b0100100;
4'b0011:fenmiao2<=7'b0110000;
4'b0100:fenmiao2<=7'b0011001;
4'b0101:fenmiao2<=7'b0010010;
4'b0110:fenmiao2<=7'b0000010;
4'b0111:fenmiao2<=7'b1111000;
4'b1000:fenmiao2<=7'b0000000;
4'b1001:fenmiao2<=7'b0010000;
default:fenmiao2<=7'b1111111;
endcase
end
endmodule
[ 本帖最后由 254677892 于 2012-12-11 08:19 编辑 ]
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