[讨论] MSP430内部寄存器BCSCTL1无法识别=。=

SYW 2015-7-10 14:23 楼主

在MSP430F5529中，BCSCTL1是一个时间的寄存器，但是为什么我的IAR在编译的时候说这个变量未定义呢？

头文件也添加过了，真是不知道为什么，查找了头文件发现确实没有这个的定义，请问各位这应该怎么办？官方的头文件在哪里可以下载到呢？

谢谢啦！

具体情况如下所示：

回复评论（3）

沙发 SYW

知道了，因为我家板子是MSP430F5529A，寄存器的名字变了，需要回去看.h文件，找找就是了。只是不知道对应IFG1的是什么。IFG1是看门狗模块里的一个“SFR中断标志寄存器”，但是.h文件中的看门狗貌似找不到对应的寄存器，这个求指点。

/************************************************************

* WATCHDOG TIMER A

************************************************************/

#define __MSP430_HAS_WDT_A__       /* Definition to show that Module is available */

#define  WDTCTL_          (0x015C)  /* Watchdog Timer Control */

DEFCW( WDTCTL          , WDTCTL_)

/* The bit names have been prefixed with "WDT" */

/* WDTCTL Control Bits */

#define WDTIS0             (0x0001)  /* WDT - Timer Interval Select 0 */

#define WDTIS1             (0x0002)  /* WDT - Timer Interval Select 1 */

#define WDTIS2             (0x0004)  /* WDT - Timer Interval Select 2 */

#define WDTCNTCL          (0x0008)  /* WDT - Timer Clear */

#define WDTTMSEL          (0x0010)  /* WDT - Timer Mode Select */

#define WDTSSEL0          (0x0020)  /* WDT - Timer Clock Source Select 0 */

#define WDTSSEL1          (0x0040)  /* WDT - Timer Clock Source Select 1 */

#define WDTHOLD          (0x0080)  /* WDT - Timer hold */

/* WDTCTL Control Bits */

#define WDTIS0_L          (0x0001)  /* WDT - Timer Interval Select 0 */

#define WDTIS1_L          (0x0002)  /* WDT - Timer Interval Select 1 */

#define WDTIS2_L          (0x0004)  /* WDT - Timer Interval Select 2 */

#define WDTCNTCL_L       (0x0008)  /* WDT - Timer Clear */

#define WDTTMSEL_L       (0x0010)  /* WDT - Timer Mode Select */

#define WDTSSEL0_L       (0x0020)  /* WDT - Timer Clock Source Select 0 */

#define WDTSSEL1_L       (0x0040)  /* WDT - Timer Clock Source Select 1 */

#define WDTHOLD_L          (0x0080)  /* WDT - Timer hold */

/* WDTCTL Control Bits */

#define WDTPW             (0x5A00)

#define WDTIS_0          (0*0x0001u)  /* WDT - Timer Interval Select: /2G */

#define WDTIS_1          (1*0x0001u)  /* WDT - Timer Interval Select: /128M */

#define WDTIS_2          (2*0x0001u)  /* WDT - Timer Interval Select: /8192k */

#define WDTIS_3          (3*0x0001u)  /* WDT - Timer Interval Select: /512k */

#define WDTIS_4          (4*0x0001u)  /* WDT - Timer Interval Select: /32k */

#define WDTIS_5          (5*0x0001u)  /* WDT - Timer Interval Select: /8192 */

#define WDTIS_6          (6*0x0001u)  /* WDT - Timer Interval Select: /512 */

#define WDTIS_7          (7*0x0001u)  /* WDT - Timer Interval Select: /64 */

#define WDTIS__2G       (0*0x0001u)  /* WDT - Timer Interval Select: /2G */

#define WDTIS__128M    (1*0x0001u)  /* WDT - Timer Interval Select: /128M */

#define WDTIS__8192K    (2*0x0001u)  /* WDT - Timer Interval Select: /8192k */

#define WDTIS__512K    (3*0x0001u)  /* WDT - Timer Interval Select: /512k */

#define WDTIS__32K       (4*0x0001u)  /* WDT - Timer Interval Select: /32k */

#define WDTIS__8192    (5*0x0001u)  /* WDT - Timer Interval Select: /8192 */

#define WDTIS__512       (6*0x0001u)  /* WDT - Timer Interval Select: /512 */

#define WDTIS__64       (7*0x0001u)  /* WDT - Timer Interval Select: /64 */

#define WDTSSEL_0       (0*0x0020u)  /* WDT - Timer Clock Source Select: SMCLK */

#define WDTSSEL_1       (1*0x0020u)  /* WDT - Timer Clock Source Select: ACLK */

#define WDTSSEL_2       (2*0x0020u)  /* WDT - Timer Clock Source Select: VLO_CLK */

#define WDTSSEL_3       (3*0x0020u)  /* WDT - Timer Clock Source Select: reserved */

#define WDTSSEL__SMLCK (0*0x0020u)  /* WDT - Timer Clock Source Select: SMCLK */

#define WDTSSEL__ACLK    (1*0x0020u)  /* WDT - Timer Clock Source Select: ACLK */

#define WDTSSEL__VLO    (2*0x0020u)  /* WDT - Timer Clock Source Select: VLO_CLK */

/* WDT-interval times [1ms] coded with Bits 0-2 */

/* WDT is clocked by fSMCLK (assumed 1MHz) */

#define WDT_MDLY_32       (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2)                      /* 32ms interval (default) */

#define WDT_MDLY_8       (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0)                /* 8ms    " */

#define WDT_MDLY_0_5       (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1)                /* 0.5ms " */

#define WDT_MDLY_0_064    (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)          /* 0.064ms " */

/* WDT is clocked by fACLK (assumed 32KHz) */

#define WDT_ADLY_1000    (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0)             /* 1000ms  " */

#define WDT_ADLY_250       (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0)       /* 250ms " */

#define WDT_ADLY_16       (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1)       /* 16ms " */

#define WDT_ADLY_1_9       (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0)  /* 1.9ms " */

/* Watchdog mode -> reset after expired time */

/* WDT is clocked by fSMCLK (assumed 1MHz) */

#define WDT_MRST_32       (WDTPW+WDTCNTCL+WDTIS2)                               /* 32ms interval (default) */

#define WDT_MRST_8       (WDTPW+WDTCNTCL+WDTIS2+WDTIS0)                         /* 8ms    " */

#define WDT_MRST_0_5       (WDTPW+WDTCNTCL+WDTIS2+WDTIS1)                         /* 0.5ms " */

#define WDT_MRST_0_064    (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)                   /* 0.064ms " */

/* WDT is clocked by fACLK (assumed 32KHz) */

#define WDT_ARST_1000    (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2)                      /* 1000ms  " */

#define WDT_ARST_250       (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0)                /* 250ms " */

#define WDT_ARST_16       (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1)                /* 16ms " */

#define WDT_ARST_1_9       (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0)          /* 1.9ms " */

/************************************************************

* Interrupt Vectors (offset from 0xFF80)

************************************************************/

点赞 2015-7-10 15:16