关于RL78的IICA读20c04的程序那个大哥有,发一个出来。
#define "r_cg_macrodriver.h"
#pragma interrupt INTIICA0 IICA_IRQHandler
typedef enum
{
WRITE_CMD_TYPE,
READ_CMD_TYPE
}IICA_CMD_TYPE;
typedef enum
[
IICA_IDLE_STATE,
IICA_SEND_SLAVE_ADDR_STATE,
IICA_SEND_DATA_ADDR_STATE,
IICA_RECEIVE_DATA_STATE,
IICA_STOP_STATE
}IICA_STATE;
typedef struct
{
IICA_STATE state;
IICA_CMD_TYPE cmdType;
uint8_t slaveAddr;
uint8_t dataAddr;
uint8_t *pbuffer;
uint16_t number;
}IICA_PARA;
volatile IICA_PARA IICA_Para;
void IICA_MasterComunicate(IICA_CMD_TYPE cmd, uint8_t slaveAddr, uint8_t dataAddr, uint8_t *pbuffer, uint16_t number)
{
uint8_t wait = 0x1F;
if (number == 0)
{
return;
}
IICA_Para.cmdType = cmd;
IICA_Para.slaveAddr = slaveAddr;
IICA_Para.dataAddr = dataAddr;
IICA_Para.pbuffer = pbuffer;
IICA_Para.number = number;
IICA_Para.state = IICA_SEND_SLAVE_ADDR_STATE;
STT0 = 1U; /* set IICA0 start condition */
IICAMK0 = 0U; /* enable INTIIA0 interrupt */
while (wait--);
IICA0 = slaveAddr; // the command is Write command for the slave address sending
}
static void __interrupt IICA_IRQHandler(void)
{
if (IICA_Para.cmdType == WRITE_CMD_TYPE)
{
IICA_MasterWrite();
}
else
{
IICA_MasterRead();
}
}
static void IICA_MasterRead(void)
{
uint8_t wait = 0x0F;
if ((1 == TRC0) && (0 == ACKD0)))
{
/* error occur, add your own code here */
IICA_Para.state = IICA_IDLE_STATE;
}
switch(IICA_Para.state)
{
case IICA_SEND_SLAVE_ADDR_STATE:
IICA0 = IICA_Para.dataAddr;
IICA_Para.state = IICA_SEND_DATA_ADDR_STATE;
break;
case IICA_SEND_DATA_ADDR_STATE:
STT0 = 1; //generate the start condition again
while (wait--); //wait a short time for the generation of start condition
IICA0 = IICA_Para.slaveAddr | 0x01;
WTIM0 = 0; //the master will genterate the interrupt at the falling edge of eighth clock
ACKE0 = 1 //enable to send ACK
IICA_Para.state = IICA_RECIEVE_DATA_STATE;
break;
case IICA_RECEIVE_DATA_STATE:
*IICA_Para.pbuffer++ = IICA0;
if (--IICA_Para.number == 0)
{
ACKE0 = 0; //the last data send the NACK. Note that the ackownlege signal is not sent untile the SCL line is released
WTIM0 = 1; //master will generate interrupt at the falling edge of the ninth clock pulse
IICA_Para.state = IICA_STOP_STATE;
} //at this time when receiving the last data, the ackownlege singal is not sent from master
WREL0 = 1; //release the SCL; Note that the master will pull down the clock after entering ingterrupt
break;
case IICA_STOP_STATE:
SPT0 = 1; IICA_Para.state = IICA_IDLE_STATE;
break;
}
}
只提供不完整的,
本帖最后由 木瓜子 于 2015-11-24 18:53 编辑