`timescale 1ns/1ns
module ypc_collect_tb();
parameter CLK50M_T=20;
parameter DATAWIDTH = 128;
parameter FIFORDWN = 8; //fifo可读数据个数宽度
parameter DMADATLEN = FIFORDWN; //DMA单次传输数据个数宽度
parameter FIFODATWIDTH = 128; //fifi数据宽度
parameter ADDRESSWIDTH=26; //BUF地址宽度
parameter BUFLENWIDTH=18; //BUF大小宽度
parameter ADCHNUM=6; //AD通道个数
parameter AD_DATWIDTH=16;
parameter BURSTCOUNTWIDTH = 8;
parameter BYTEE_NABLEWIDTH = 16;
parameter ADDR_DMACON = 0;
parameter ADDR_DMASTATE = ADDR_DMACON+1;
parameter ADDR_DMAINTMASK = ADDR_DMASTATE+1;
parameter ADDR_DMAINTCLEAR = ADDR_DMAINTMASK+1;
parameter ADDR_DMAINTSTATE = ADDR_DMAINTCLEAR+1;
parameter ADDR_BUFBASE_CH0 = ADDR_DMAINTSTATE+1;
parameter ADDR_BUFLEN_CH0 = ADDR_BUFBASE_CH0+1;
parameter ADDR_BUFBASE_CH1 = ADDR_BUFLEN_CH0+1;
parameter ADDR_BUFLEN_CH1 = ADDR_BUFBASE_CH1+1;
parameter ADDR_BUFBASE_CH2 = ADDR_BUFLEN_CH1+1;
parameter ADDR_BUFLEN_CH2 = ADDR_BUFBASE_CH2+1;
parameter ADDR_BUFBASE_CH3 = ADDR_BUFLEN_CH2+1;
parameter ADDR_BUFLEN_CH3 = ADDR_BUFBASE_CH3+1;
parameter ADDR_BUFBASE_CH4 = ADDR_BUFLEN_CH3+1;
parameter ADDR_BUFLEN_CH4 = ADDR_BUFBASE_CH4+1;
parameter ADDR_BUFBASE_CH5 = ADDR_BUFLEN_CH4+1;
parameter ADDR_BUFLEN_CH5 = ADDR_BUFBASE_CH5+1;
parameter ADDR_COLECT_CON = ADDR_BUFLEN_CH5+1;
parameter ADDR_COLECT_STATE = ADDR_COLECT_CON+1;
parameter ADDR_COLECT_CONCH0 = ADDR_COLECT_STATE+1;
parameter ADDR_COLECT_TRIGDAT0 = ADDR_COLECT_CONCH0+1;
parameter ADDR_COLECT_PRETRIGBUF0 = ADDR_COLECT_TRIGDAT0+1;
parameter ADDR_COLECT_ENDPOS0 = ADDR_COLECT_PRETRIGBUF0+1;
parameter ADDR_COLECT_TRIGPOS0 = ADDR_COLECT_ENDPOS0+1;
parameter ADDR_COLECT_CONCH1 = ADDR_COLECT_TRIGPOS0+1;
parameter ADDR_COLECT_TRIGDAT1 = ADDR_COLECT_CONCH1+1;
parameter ADDR_COLECT_PRETRIGBUF1 = ADDR_COLECT_TRIGDAT1+1;
parameter ADDR_COLECT_ENDPOS1 = ADDR_COLECT_PRETRIGBUF1+1;
parameter ADDR_COLECT_TRIGPOS1 = ADDR_COLECT_ENDPOS1+1;
parameter ADDR_COLECT_CONCH2 = ADDR_COLECT_TRIGPOS1+1;
parameter ADDR_COLECT_TRIGDAT2 = ADDR_COLECT_CONCH2+1;
parameter ADDR_COLECT_PRETRIGBUF2 = ADDR_COLECT_TRIGDAT2+1;
parameter ADDR_COLECT_ENDPOS2 = ADDR_COLECT_PRETRIGBUF2+1;
parameter ADDR_COLECT_TRIGPOS2 = ADDR_COLECT_ENDPOS2+1;
parameter ADDR_COLECT_CONCH3 = ADDR_COLECT_TRIGPOS2+1;
parameter ADDR_COLECT_TRIGDAT3 = ADDR_COLECT_CONCH3+1;
parameter ADDR_COLECT_PRETRIGBUF3 = ADDR_COLECT_TRIGDAT3+1;
parameter ADDR_COLECT_ENDPOS3 = ADDR_COLECT_PRETRIGBUF3+1;
parameter ADDR_COLECT_TRIGPOS3 = ADDR_COLECT_ENDPOS3+1;
parameter ADDR_COLECT_CONCH4 = ADDR_COLECT_TRIGPOS3+1;
parameter ADDR_COLECT_TRIGDAT4 = ADDR_COLECT_CONCH4+1;
parameter ADDR_COLECT_PRETRIGBUF4 = ADDR_COLECT_TRIGDAT4+1;
parameter ADDR_COLECT_ENDPOS4 = ADDR_COLECT_PRETRIGBUF4+1;
parameter ADDR_COLECT_TRIGPOS4 = ADDR_COLECT_ENDPOS4+1;
parameter ADDR_COLECT_CONCH5 = ADDR_COLECT_TRIGPOS4+1;
parameter ADDR_COLECT_TRIGDAT5 = ADDR_COLECT_CONCH5+1;
parameter ADDR_COLECT_PRETRIGBUF5 = ADDR_COLECT_TRIGDAT5+1;
parameter ADDR_COLECT_ENDPOS5 = ADDR_COLECT_PRETRIGBUF5+1;
parameter ADDR_COLECT_TRIGPOS5 = ADDR_COLECT_ENDPOS5+1;
reg clk_50M;
reg rst;
reg [31:0] s_wdata;
reg [5:0] s_addr;
wire [31:0] s_rdata;
reg s_chipselect;
reg s_read;
reg s_write;
reg [3:0] s_byteenable;
wire s_int;
reg m_clk;
reg master_waitrequest;
wire [ADDRESSWIDTH-1:0] master_address;
wire master_write;
wire [BYTEE_NABLEWIDTH-1:0] master_byteenable;
wire [DATAWIDTH-1:0] master_writedata;
wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
wire master_burstbegin;
wire [AD_DATWIDTH-1:0] ADdat;
wire ADen;
integer read_dat;
always #(CLK50M_T/2) clk_50M = ~clk_50M;
always #(CLK50M_T/4) m_clk = ~m_clk;
initial
begin
clk_50M=0;
m_clk=0;
read_dat=0;
rst=0;
s_wdata=0;
s_addr=0;
s_chipselect=0;
s_read=0;
s_write=0;
s_byteenable=-1;
master_waitrequest=0;
rst_task();
init_task();
int_task();
#(CLK50M_T*10000);
$stop;
#(CLK50M_T*10000);
$stop;
#(CLK50M_T*10000);
$stop;
#(CLK50M_T*10000);
$stop;
end
task int_task;
begin
forever
begin
@(posedge clk_50M)
if(s_int)
begin
set_dmaintclear();
#(CLK50M_T*20);
@( posedge clk_50M);
if(read_dat&8'h01)
en_DMAch(8'h01);
@( posedge clk_50M);
if(read_dat&8'h02)
en_DMAch(8'h02);
@( posedge clk_50M);
if(read_dat&8'h04)
en_DMAch(8'h04);
@( posedge clk_50M);
if(read_dat&8'h08)
en_DMAch(8'h08);
@( posedge clk_50M);
if(read_dat&8'h10)
en_DMAch(8'h10);
@( posedge clk_50M);
if(read_dat&8'h20)
en_DMAch(8'h20);
end
end
end
endtask
task rst_task;
begin
#(CLK50M_T*100)
rst=1;
#(CLK50M_T*100)
rst=0;
#(CLK50M_T*10);
end
endtask
task init_task;
begin
chbuf_init();
collect_init();
set_dmacon(8'h3f,1); //使能DMA
set_dmaintmask(8'h3f); //开中断
end
endtask
task en_DMAch;
input [7:0] ench;
begin
set_dmacon(ench,1);
end
endtask
task set_dmaintclear;
begin
avl_read(ADDR_DMAINTSTATE);
avl_write(ADDR_DMAINTCLEAR,{24'd0,read_dat[7:0]});
//avl_write(ADDR_DMAINTMASK,{24'd0,intmask});
@( posedge clk_50M);
s_write=0;
s_read=0;
s_chipselect=0;
end
endtask
task set_dmaintmask;
input [7:0] intmask;
begin
avl_write(ADDR_DMAINTCLEAR,{24'd0,8'hff});
avl_write(ADDR_DMAINTMASK,{24'd0,intmask});
@( posedge clk_50M);
s_write=0;
s_chipselect=0;
end
endtask
task set_dmacon;
input [7:0] channel_en;
input doen;
begin
avl_write(ADDR_DMACON,{23'd0,doen,channel_en});
avl_write(ADDR_COLECT_CON,{24'd0,channel_en});
@( posedge clk_50M);
s_write=0;
s_chipselect=0;
end
endtask
task collect_init;
begin
set_chcollect(ADDR_COLECT_CONCH0,9,0,256,100);
set_chcollect(ADDR_COLECT_CONCH1,10,1,256,100);
set_chcollect(ADDR_COLECT_CONCH2,11,2,256,100);
set_chcollect(ADDR_COLECT_CONCH3,12,3,256,100);
set_chcollect(ADDR_COLECT_CONCH4,13,2,256,100);
set_chcollect(ADDR_COLECT_CONCH5,14,1,256,100);
end
endtask
task chbuf_init;
begin
set_chbuf(ADDR_BUFBASE_CH0,0,'h200);
set_chbuf(ADDR_BUFBASE_CH1,'h200,'h200);
set_chbuf(ADDR_BUFBASE_CH2,'h400,'h200);
set_chbuf(ADDR_BUFBASE_CH3,'h600,'h200);
set_chbuf(ADDR_BUFBASE_CH4,'h800,'h200);
set_chbuf(ADDR_BUFBASE_CH5,'hA00,'h200);
end
endtask
task set_chcollect;
input [5:0] avl_Address;
input [7:0] freqdiv;
input [23:0] trig_type;
input [31:0] trigdat;
input [31:0] pre_cachsize;
begin
avl_write(avl_Address,{trig_type,freqdiv});
avl_write(avl_Address+1,trigdat);
avl_write(avl_Address+2,pre_cachsize);
@( posedge clk_50M);
s_write=0;
s_chipselect=0;
end
endtask
task set_chbuf;
input [5:0] avl_Address;
input [31:0] buf_base_addr;
input [31:0] buf_length;
begin
avl_write(avl_Address,buf_base_addr);
avl_write(avl_Address+1,buf_length);
@( posedge clk_50M);
s_write=0;
s_chipselect=0;
end
endtask
task avl_write;
input [5:0] avl_Address;
input [31:0] avl_wdat;
begin
@( posedge clk_50M);
s_addr=avl_Address;
s_wdata=avl_wdat;
s_write=1;
s_read=0;
s_chipselect=1;
end
endtask
task avl_read;
input [5:0] avl_Address;
begin
@( posedge clk_50M);
s_addr=avl_Address;
s_read=1;
s_write=0;
s_chipselect=1;
@( posedge clk_50M);
@( posedge clk_50M);
read_dat=s_rdata;
s_chipselect=0;
s_read=0;
end
endtask
ypc_collect ypc_collect_t
(
.clk_50M(clk_50M),
.s_clk(clk_50M),
.rst(rst),
.s_wdata(s_wdata),
.s_addr(s_addr),
.s_rdata(s_rdata),
.s_chipselect(s_chipselect),
.s_read(s_read),
.s_write(s_write),
.s_byteenable(s_byteenable),
.s_int(s_int),
.m_clk(m_clk),
.master_waitrequest(master_waitrequest),
.master_address(master_address),
.master_write(master_write),
.master_byteenable(master_byteenable),
.master_writedata(master_writedata),
.master_burstcount(master_burstcount),
.master_burstbegin(master_burstbegin),
.ADdat_0(ADdat),
.ADen_0(ADen),
.ADdat_1(ADdat),
.ADen_1(ADen),
.ADdat_2(ADdat),
.ADen_2(ADen),
.ADdat_3(ADdat),
.ADen_3(ADen),
.ADdat_4(ADdat),
.ADen_4(ADen),
.ADdat_5(ADdat),
.ADen_5(ADen)
);
adsinger adsinger_t
(
.clk(clk_50M),
.rst(rst),
.ADdat(ADdat),
.ADen(ADen)
);
endmodule
yupc123，你好
这是一个比较有参考价值的tb。
大家参照这个来写，可以节约很多 不必要的弯路，和语法上纠结。
几点小建议：
task的明名，全用task_开头，或t_开头
task间空行
代码里面的空格代码对齐
还可以在整理整理，按功能模块来写
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