[求助] 总线收发器SN74AVC20T245名字的意义

SN74AVC20T245总线收发器中各个字母和数字的含义是什么，求大佬们告知。

这要看是哪个厂家生产的吧？不同厂家含义或许有些差别

以下TI的定义，转

TI有很多的逻辑产品，很多型号命名看起来相差很小，有时候就多一个字母，或少一个字母而已，比如SN74LVC162244，SN74LVCH162244，以

以SN   74    LVC    H    16    2    244   A    DGG    R   E4为例来具体说明一下：

1 .Standard Prex

Examples: SN  Standard Prefix
SNJ  Conforms to MIL-PRF-38535 (QML)

2. Temperature Range

Examples: 54  Military
74  Commercia

3 .Family

Examples: Blank – Transistor-Transistor Logic (TTL)
ABT  Advanced BiCMOS Technology
ABTE/ETL  Advanced BiCMOS Technology/
Enhanced Transceiver Logic
AC/ACT  Advanced CMOS Logic
AHC/AHCT  Advanced High-Speed CMOS Logic
ALB  Advanced Low-Voltage BiCMOS
ALS  Advanced Low-Power Schottky Logic
ALVC  Advanced Low-Voltage CMOS Technology
ALVT  Advanced Low-Voltage BiCMOS Technology
AS  Advanced Schottky Logic
AUC  Advanced Ultra-Low-Voltage CMOS Logic
AUP  Advanced Ultra-Low-Power CMOS Logic
AVC  Advanced Very Low-Voltage CMOS Logic
BCT  BiCMOS Bus-Interface Technology
CB3Q  2.5-V/3.3-V Low-Voltage High-Bandwidth
Bus-Switch Crossbar Technology Logic
CB3T  2.5-V/3.3-V Low-Voltage Translator
Bus-Switch Crossbar Technology Logic
CBT  Crossbar Technology
CBT-C  5-V Bus-Switch Crossbar Technology
Logic With ㈢-V Undershoot Protection
CBTLV  Low-Voltage Crossbar Technology Logic
F  F Logic
FB  Backplane Transceiver Logic/Futurebus+
GTL  Gunning Transceiver Logic
GTLP  Gunning Transceiver Logic Plus
HC/HCT  High-Speed CMOS Logic
HSTL  High-Speed Transceiver Logic
LS  Low-Power Schottky Logic
LV-A  Low-Voltage CMOS Technology
LV-AT  Low-Voltage CMOS Technology –
TTL Compatible
LVC  Low-Voltage CMOS Technology
LVT  Low-Voltage BiCMOS Technology
PCA/PCF  I2C Inter-Integrated Circuit Applications
S  Schottky Logic
SSTL  Stub Series-Terminated Logic
SSTU  Stub Series-Terminated Ultra-Low-Voltage Logic
SSTV/SSTVF  Stub Series-Terminate Low-Voltage Logic
TVC  Translation Voltage Clamp Logic
VME  VERSAmodule Eurocard Bus Technology

4 Special Features
Examples: Blank = No Special Features
C  Configurable VCC (LVCC)
D  Level-Shifting Diode (CBTD)
H  Bus Hold (ALVCH) Circuitry (CBTK)
K  Undershoot-Protection Ports (LVCR)
R  Damping Resistor on Both Output
S  Schottky Clamping Diode (CBTS)
Z  Power-Up 3-State (LVCZ)


5 Bit Width
Examples: Blank = Gates, MSI, and Octals
1G  Single Gate
2G  Dual Gate
3G  Triple Gate
8  Octal IEEE 1149.1 (JTAG)
16  Widebus (16-, 18- and 20-bit)
18  Widebus IEEE 1149.1 (JTAG)
32  Widebus+ (32- and 36-bit)


6 Options
Examples: Blank = No Options Output Port
2  Series Damping Resistor on One
4  Level Shifter
25  25-Ω Line Driver


7 Function
Examples: 244  Noninverting Buffer/Driver
374  D-Type Flip-Flop
573  D-Type Transparent Latch
640  Inverting Transceiver


8 Device Revision
Examples: Blank = No Revision
Letter Designator A娢

9 Packages
Commercial: D, DW  Small-Outline Integrated Circuit (SOIC)
DB, DBQ, DCT, DL  Shrink Small-Outline Package
(SSOP)
DBB, DGV  Thin Very Small-Outline Package (TVSOP)
DBQ  Quarter-Size Small-Outline Package (QSOP)
DBV, DCK, DCY, PK  Small-Outline Transistor (SOT)
DCU  Very Thin Shrink Small-Outline Package (VSSOP)
DGG, PW  Thin Shrink Small-Outline Package (TSSOP)
FN  Plastic Leaded Chip Carrier (PLCC)
GGM, GKE, GKF, ZKE, ZKF  MicroStar BGATM
Low-Profile Fine-Pitch Ball Grid Array (LFBGA)
GQL, GQN, ZQL, ZQN, ZXU, ZXY  MicroStar JunioTM
Very-Thin-Profile Fine-Pitch Ball Grid Array (VFBGA)
N, NT, P  Plastic Dual-In-Line Package (PDIP)
NS, PS  Small-Outline Package (SOP)
PAG, PAH, PCA, PCB, PM, PN, PZ  Thin Quad
Flatpack (TQFP)
PH, PQ, RC  Quad Flatpack (QFP)
PZA  Low-Profile Quad Flatpack (LQFP)
RGQ, RGY, DRY, RSE, RSW, DRJ, DRC, RGE
Quad Flatpack No Lead (QFN)
YZP  NanoStarTM and NanoFreeTM Die-Size
Ball Grid Array (DSBGA)
Military: FK  Leadless Ceramic Chip Carrier (LCCC)
GB  Ceramic Pin Grid Array (CPGA)
HFP, HS, HT, HV  Ceramic Quad Flatpack (CQFP)
J, JT  Ceramic Dual-In-Line Package (CDIP)
W, WA, WD  Ceramic Flatpack (CFP)


10 Tape and Reel
R  Tape and reel packing (standard reel quantities)
T  Tape and reel packing (short reel, 250 units)


11 RoHS and Green Status
E_ – Conforms to JEDEC JESD97 E-Category specification for
Pb-free and reduced environmentally unfriendly substances
G_ – Additional reductions in environmentally unfriendly substances
(Sb and Br) in addition to E_ reductions
DSBGA is the JEDEC reference for wafer chip scale package (WCSP).