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HiperPFS-4

Family

PFC Controller with Integrated 600 V MOSFET and Diode Option

Optimized for High PF and Efficiency Across Load Range

Key Benefits

•

High efficiency and power factor across load range

•

>95% efficiency from 10% load to 100% load

•

<60 mW no-load consumption at 230 VAC

•

PF >0.95 achievable at 20% load for H and L packages

•

Programmable Power Good (PG) signal

•

Digital line peak detection for robust performance even with

distorted input voltage from UPS or generators

•

Digital power factor enhancer compensates for EMI filter and bridge

distortion

•

Spread-spectrum across >60 kHz window simplifies EMI filtering

•

Protection features include: UVLO, UV, OV, OTP, brown-in/out, cycle-

by-cycle current limit and power limiting for overload protection

•

Withstands 305 VAC steady-state and 410 VAC abnormal input

•

Eliminates insulating pad/heat-spreader

HiperPFS-4

VCC

CONTROL

VCC

PGT

OUT

REF

PI-7965-100318

Figure 1a. Typical Application Schematic without Integrated Diode

Applications

•

Printer

LCD TV

Video game consoles

80 Plus™ Platinum

designs

•

High-power adaptors

•

High-power LED lighting

•

Industrial and appliance

•

Generic PFC converters

CONTROL

VCC

HiperPFS-4

PGT

OUT

REF

PI-7224a-042720

Figure 1b. Typical Application Schematic with Integrated Diode

InSOP-24B (C Package)

Figure 2.

eSIP-16D (H Package)

eSIP-16G (L Package)

Package Options.

Body Dimensions: 10.8 mm x 9.4 mm for C Package and

16.53 mm x 8.25 mm for H & L Packages.

www.power.com

August 2020

This Product is Covered by Patents and/or Pending Patent Applications.

PFS7x23-7x29/7633-7636

Output Power Table

Universal Input Devices (C Package) Without Integrated Diode

Product

PFS7623C

PFS7624C

PFS7626C

PFS7628C

Continuous Output Power at 90 VAC

75 W

90 W

105 W

110 W

Universal Input Devices (H and L Packages)

Without Integrated Diode

Product

PFS7623H/L

PFS7624H/L

PFS7625H/L

PFS7626H/L

PFS7627H/L

PFS7628H/L

PFS7629H/L

Continuous

Output Power at

90 VAC

110 W

130 W

185 W

230 W

290 W

350 W

405 W

Peak Output Power

120 W

150 W

205 W

260 W

320 W

385 W

450 W

High-Line Input Only Devices (H Package)

Without Integrated Diode

Product

PFS7633H

PFS7634H

PFS7635H

PFS7636H

Continuous

Output Power at

180 VAC

255 W

315 W

435 W

550 W

Peak Output

Power

280 W

350 W

480 W

610 W

Universal Input Devices With Integrated Diode

Maximum Continuous

Output Power Rating

at 90 VAC

(Full Power Mode)

110 W

130 W

185 W

230 W

290 W

350 W

405 W

Peak Output Power

(Full Power Mode)

120 W

150 W

205 W

260 W

320 W

385 W

450 W

Product

PFS7723L/H

PFS7724L/H

PFS7725L/H

PFS7726H

PFS7727H

PFS7728H

PFS7729H

Table 1.

Output Power Table (See Table 2 on page 12 for Maximum Continuous

Output Power Ratings.)

Rev. F 08/20

www.power.com

PFS7x23-7x29/7633-7636

Description

The HiperPFS™-4 devices incorporate a continuous conduction mode

(CCM) boost PFC controller, gate driver and 600 V power MOSFET in a

single, low-profile (GROUND pin connected) power package. HiperPFS-4

devices eliminate need for external current sense resistors and their

associated power loss, and use an innovative control technique that

adjusts the switching frequency over output load, input line voltage,

and input line cycle.

This control technique maximizes efficiency over the entire load range,

particularly at light loads. Additionally, it minimizes the EMI filtering

requirements due to its wide bandwidth spread spectrum effect. The

HiperPFS-4 uses advanced digital techniques for line monitoring, line

feed-forward scaling, and power factor enhancement; while using

analog techniques for the core controller in order to maintain extremely

low no-load power consumption. The HiperPFS-4 also features an

integrated non-linear error amplifier for enhanced load transient

response, a user programmable Power Good (PG) signal as well as user

selectable power limit functionality. HiperPFS-4 includes Power

Integrations’ standard set of comprehensive protection features, such

as UV, OV, brown-in/out, and hysteretic thermal shutdown. HiperPFS-4

also provides cycle-by-cycle current limit and Safe Operating Area

(SOA) protection of the power MOSFET, output power limiting for

overload protection, and pin-to-pin short-circuit protection

HiperPFS-4’s innovative variable frequency continuous conduction

mode operation (VF-CCM) minimizes switching losses by maintaining a

low average switching frequency, while modulating the switching

frequency in order to suppress EMI, the traditional challenge with

continuous conduction mode solutions. Systems using HiperPFS-4

typically reduce the total X and Y capacitance requirements of the

converter, the inductance of both the boost choke and EMI noise

suppression chokes, thereby reducing overall system size and cost.

Additionally, HiperPFS-4 devices dramatically reduce component count

and board footprint while simplifying system design and enhancing

reliability, when compared with designs that use discrete MOSFETs and

controllers. The innovative variable frequency, continuous conduction

mode controller enables the HiperPFS-4 to realize all of the benefits of

continuous conduction mode operation while leveraging low-cost,

small, simple EMI filters.

Many regions mandate high power factor for many electronic products

with high power requirements. These rules are combined with

numerous application-specific standards that require high power supply

efficiency across the entire load range, from full load to as low as 10%

load. High efficiency at light load is a challenge for traditional PFC

solutions where fixed MOSFET switching frequencies cause fixed

switching losses on each cycle, even at light loads. In addition to

featuring flat efficiency across the load range, HiperPFS-4 also enables

a high power factor of >0.95 at 20% load. HiperPFS-4 simplifies

compliance with new and emerging energy-efficiency standards over a

broad market space in applications such as PCs, LCD TVs, notebooks,

appliances, pumps, motors, fans, printers and LED lighting.

HiperPFS-4’s advanced power packaging technology and high

efficiency simplify the complexity of mounting the IC and thermal

management, while providing very high power capabilities in a single

compact package; these devices are suitable for PFC applications with

maximum continuous power from 75 W to 405 W universal (550 W

high-line only).

Accurate built-in undervoltage (UV) protection.

Accurate built-in overvoltage (OV) protection.

Hysteretic thermal shutdown (OTP).

Internal power limiting function for overload protection.

Cycle-by-cycle power-switch current limit.

Internal non-linear error amplifier for enhanced load transient

response

No external current sense resistor required.

•

Provides ‘lossless’ internal sensing via sense-FET.

•

Reduces component count and system losses.

•

Minimizes high current gate drive loop area.

Minimizes output overshoot and stresses during start-up

•

Integrated power limit.

Improved dynamic response.

•

Digitally controlled input line feed-forward gain adjustment for

flattened loop gain across entire input voltage range.

Eliminates up to 39 discrete components for higher reliability and

lower cost.

•

Solution for High Efficiency, Low EMI and High PF

•

Continuous conduction mode PFC uses novel constant amp-second

[on-time] volt-second [off-time] control.

•

High efficiency across load.

•

High power factor across load.

•

Frequency sliding technique for light load efficiency improvements.

•

>95% efficiency from 10% load to full load achievable at

nominal input voltages.

•

Variable switching frequency to simplify EMI filter design.

•

Varies over line input voltage to maximize efficiency and

minimize EMI filter requirements.

•

Varies with input line cycle voltage by >60 kHz to maximize

spread spectrum effect.

Advanced Package for High Power Applications

(H & L Packages)

•

Up to 450 W [universal], 610 W [high-line only] peak output power

capability in a highly compact package.

•

Simple adhesive or clip mounting to heat sink.

•

No insulation pad required and can be directly connected to

heat sink.

•

Staggered pin arrangement allows simple routing of board traces

and to meet high-voltage creepage requirements.

•

Single package solution for PFC converter reduces assembly costs

and layout size.

SMD Package (C Package)

•

Allows the elimination of metal heat sink.

•

Use PCB copper foil for heat dissipation.

Pin Functional Description

BIAS POWER (VCC) Pin

This is a 10.2-15 VDC [12 V typical] bias supply used to power the IC.

The bias voltage must be externally clamped to prevent the BIAS

POWER pin from exceeding 15 VDC to ensure long-term reliability

REFERENCE (REF) Pin

This pin is connected to an external bypass capacitor and is used to

program the IC for either FULL or EFFICIENCY power mode. The

external capacitor is connected between the REFERENCE and SIGNAL

GROUND [G] pins. Note: the return trace to the ground pin must not

be shared with other return traces that may pass large return

currents during surge events. The REFERENCE pin has two valid

capacitor values to select ‘Full’ (1.0

±20%) or ‘Efficiency’ (0.1

±20%) power modes.

SIGNAL GROUND (G) Pin

Discrete components used in the feedback circuit, including loop

compensation, decoupling capacitors for the BIAS POWER (VCC),

REFERENCE (REF) and VOLTAGE MONITOR (V) must be referenced to

Product Highlights

Protected Power Factor Correction Solution

•

Incorporates 600 V power MOSFET, controller and gate driver.

•

EN61000-3-2 Class C and Class D compliance.

•

Integrated protection features reduce external component count

•

Accurate built-in brown-in/out protection.

www.power.com

Rev. F 08/20

PFS7x23-7x29/7633-7636

the SIGNAL GROUND (G) pin. The SIGNAL GROUND pin is also

connected to the tab of the device. The SIGNAL GROUND pin should

not be tied directly to the SOURCE pin external to the IC.

VOLTAGE MONITOR (V) Pin

The VOLTAGE MONITOR pin is tied to the rectified high-voltage DC

rail through a 100:1, 1% high-impedance resistor divider to minimize

power dissipation and standby power consumption. The recommended

resistance value is between 8 MW and 16 MW. Changing this divider

ratio affects peak power limit, brown-in/out thresholds and will

degrade input current quality (reduce power factor and increase

THD). A small ceramic capacitor forming an 80

nominal time-

constant must be connected between the VOLTAGE MONITOR pin to

the SIGNAL GROUND pin to bypass any switching noise present on

the rectified DC bus.

This pin also features brown-in/out detection thresholds and

incorporates a weak current source that acts as a pull-down in the

event of an open circuit condition.

COMPENSATION (C) Pin

This pin is used for loop pole/zero compensation of the OTA error

amplifier via the connection of a network of capacitors and a resistor

between the COMPENSATION pin and SIGNAL GROUND pin. The

COMPENSATION pin connects internally to the output of the OTA

error amplifier and the input to the on-time and off-time controllers.

FEEDBACK (FB) Pin

This pin is connected to the main voltage regulation feedback resistor

divider network and is also used for fast over and undervoltage

protection. This pin also detects the presence of the feedback

voltage divider network at start-up and during operation. The divider

ratio should be the same as the VOLTAGE MONITOR pin for proper

and optimized power limit and power factor. A large upper resistor

between 8 MW and 16 MW ±1% is recommended. A small ceramic

capacitor between FEEDBACK and SIGNAL GROUND, forming a

nominal 80

time-constant with the bottom resistor, is required.

POWER GOOD (PG) Pin

Use of the PG function is optional. The POWER GOOD pin is an

active low, open-drain connection which sinks current when the

output voltage is in regulation. At start-up, once the FEEDBACK pin

voltage has risen to ~95% of the internal reference voltage, the

POWER GOOD pin is asserted low.

After start-up, the output voltage threshold at which the PG signal

becomes high-impedance depends on the threshold programmed by

the POWER GOOD THRESHOLD pin resistor. When not used, the

POWER GOOD pin is left unconnected.

POWER GOOD THRESHOLD (PGT) Pin

This pin is used to program the output voltage threshold at which the

PG signal becomes high-impedance representing the PFC stage falling

out of regulation. The low threshold for the PG signal is programmed

with a resistor between the POWER GOOD THRESHOLD and SIGNAL

GROUND pins. Tying the POWER GOOD THRESHOLD to the

REFERENCE pin disables the power good function (i.e. POWER GOOD

pin remains high impedance).

SOURCE (S) Pins

These pins are the source connection of the power switch as well as

the negative bulk capacitor terminal connection.

DRAIN (D) Pin

This is the drain connection of the internal power switch.

Boost Diode Cathode (K) Pin

This is the cathode connection of the internal Qspeed diode.

L Package (eSIP-16G)

(Front View)

H Package (eSIP-16D)

(Front View)

H Package (eSIP-16D)

(Back View)

Exposed Pad (Backside of

Both H and L Packages)

Internally Connected to

GROUND (G) Pin

Pin 1 I.D.

8 10

Exposed Pad

(Backside)

Not Shown

VCC

3 4 5 6 7 8 910 11 1314 16

PGT

REF

NC 13

NC 14

NC 15

D 16-19

S 24

NC/K

16 14 13 1110 9 8 7 6 5 4 3

NC/K

REF

PGT

REF

VCC

Exposed Pad

Connected to

DRAIN (D) Pin

Note pin 16 is NC for PFS76xx and K pin for PFS772x.

REF

NC/K

9 11

PGT

C Package (InSOP-24B)

(Top View)

C Package (InSOP-24B)

(Bottom View)

PI-8616-081320

Figure 3.

Pin Configuration.

Rev. F 08/20

www.power.com

PFS7x23-7x29/7633-7636

DRAIN (D)

BOOST DIODE CATHODE (K)

BIAS POWER (VCC)

VOLTAGE MONITOR (V)

INPUT LINE INTERFACE

ADC

PEAK

DETECTOR

ENHANCER

LOW/HIGH

LINE DETECT

12 V GATE DRIVER

REF SERIES/SHUNT

REGULATOR

Integrated Qspeed

Ultrafast Diode

(Diode option in PFS772xH/L only)

UVLO

BROWN-IN/

OUT DETECT

BO, BI

Off-Time Controller

OFF

- V

)

INT

~(V

O-

)

HL/LL

ON(PFE)

OCP

REFERENCE

(REF)

BRST

REF

PG(H)

OFF

VCC

REFERENCE

AND BAND GAP

PGT

OFF

is a function of the error-voltage

) and is used to reduce

the average operating frequency

as a function of output power

TIMER

SUPERVISOR

Latch

FEEDBACK Pin

OV/UV/OFF

Power

MOSFET

senseFET

VCC

OFF

Feedback OV

OFF

Frequency

Slide

HL/LL

Non-Linear OTA

REF

FEEDBACK

(FB)

Feedback UV

Buffer and

De-Glitch

Filter

SNS

LEB

OCP

OTA

OCP

POWER LIMIT

SOA RAMP

HL/LL

BRST

Feedback OFF

On-Time Controller

INT

ON(PFE)

SNS

ON(PFE)

is the switch

current sense scale

factor which is a function

of the peak input voltage

START-UP,

FMEA CHECKS

OFF

PG(H)

REF

PGT

POWER GOOD

THRESHOLD

(PGT)

POWER GOOD

(PG)

SOURCE (S)

SIGNAL GROUND (G)

COMPENSATION (C)

PI-7969a-081920

Figure 4.

Functional Block Diagram.

Functional Description

The HiperPFS-4 family are variable switching frequency boost PFC

devices. It employs a constant amp-second on-time and constant

volt-second off-time control algorithm. This algorithm is used to

regulate the output voltage and shape the input current to comply

with regulatory harmonic current limits (high power factor). Integrat-

ing the switch current and controlling it to have a constant amp-sec

product over the on-time of the switch allows the average input

current to follow the input voltage. Integrating the difference

between the output and input voltage maintains a constant volt-

second balance dictated by the electro-magnetic properties of the

boost inductor and thus regulates the output voltage and power.

More specifically, the control technique sets constant volt-seconds for

the off-time (t

OFF

). The off-time is controlled such that:

The controller also sets a constant value of charge delivered during

each on-cycle of the power MOSFET. The charge per cycle is varied

gradually over many switching cycles in response to load changes so

it can be considered constant for a half line cycle. With this constant

charge (or amp-second) control, the following relationship is therefore

also true:

Substituting t

from (2) into (3) gives:

(3)

(4)

Since the volt-seconds during the on-time must equal the volt-

seconds during the off-time, to maintain flux equilibrium in the PFC

choke, the on-time (t

) is controlled such that

OFF

(1)

The relationship of (4) demonstrates that by controlling a constant

amp-second on-time and constant volt-second off-time, the input

current I

is proportional to the input voltage V

, therefore providing

the fundamental requirement of power factor correction.

This control produces a continuous mode power switch current

waveform that varies both in frequency and peak current value across

a line half-cycle to produce an input current proportional to the input

voltage.

(2)

www.power.com

Rev. F 08/20