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STM32H743VIH6TR

ARM® Cortex®-M7 series 微控制器 IC 32-位 480MHz 2MB(2M x 8) 闪存 100-TFBGA(8x8)

产品类别:半导体    嵌入式处理器和控制器   

制造商:ST(意法半导体)

官网地址:http://www.st.com/

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STM32H743VIH6TR概述
STM32H743VIH6是一种高性能的Arm®Cortex®-M7 32位RISC核心,工作频率高达480MHz。Cortex®-M7核心有一个浮点单元(FPU),支持Arm®双精度(IEEE754兼容)和单精度数据处理指令和数据类型。STM32H743VIH6器件支持全套DSP指令和内存保护单元(MPU),提高应用安全性。STM32H743VIH6器件采用高速嵌入式存储器,具有最大2mbytes的双排Flash存储器,最大1mbyte的RAM(包括192kbybytes的TCMRAM),最大864kbytes的用户SRAM和4kbytes的用户SRAM,最大864kbytes的用户SRRAM,最大864kbyxbytes的用户SRRAM,最大864kbysbyxbytes的用户SRRARAAM,以及广泛的增强I/O和外设,连接到APB总线、AHB总线、2x32-bit的多AHB总线矩阵和支持内部和外部存储器访问的多层axis互连。

STM32H743VIH6提供3个adc、2个dac、2个超低功耗比较器、1个低功耗RTC、1个高分辨率定时器、12个通用16位定时器、2个电机控制的PWM定时器、5个低功耗定时器和一个真正的随机数发生器(RNG)。该装置支持四个数字滤波器,用于外部sigma-delta调制器(DFSDM)。它们还具有标准和高级通信接口。
STM32H743VIH6TR规格参数
参数名称
属性值
类别
半导体;嵌入式处理器和控制器
厂商名称
ST(意法半导体)
系列
STM32H7
包装
卷带(TR)
核心处理器
ARM® Cortex®-M7
内核规格
32 位单核
速度
480MHz
连接能力
CANbus,EBI/EMI,以太网,I²C,IrDA,LINbus,MDIO,MMC/SD/SDIO,QSPI,SAI,SPDIF,SPI,SWPMI,UART/USART,USB OTG
外设
欠压检测/复位,DMA,I²S,LCD,POR,PWM,WDT
I/O 数
82
程序存储容量
2MB(2M x 8)
程序存储器类型
闪存
RAM 大小
1M x 8
电压 - 供电 (Vcc/Vdd)
1.71V ~ 3.6V
数据转换器
A/D 36x16b; D/A 2x12b
振荡器类型
内部
工作温度
-40°C ~ 85°C(TA)
安装类型
表面贴装型
封装/外壳
100-TFBGA
供应商器件封装
100-TFBGA(8x8)
基本产品编号
STM32H743
STM32H743VIH6TR文档预览
STM32H742xI/G STM32H743xI/G
32-bit Arm
®
Cortex
®
-M7 480MHz MCUs, up to 2MB Flash,
up to 1MB RAM, 46 com. and analog interfaces
Datasheet
-
production data
Features
Includes ST state-of-the-art patented
technology
Core
32-bit Arm
®
Cortex
®
-M7 core with double-
precision FPU and L1 cache: 16 Kbytes of data
and 16 Kbytes of instruction cache; frequency
up to 480 MHz, MPU, 1027 DMIPS/
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
LQFP100
(14 x 14 mm)
LQFP144
(20 x 20 mm)
LQFP176
(24 x 24 mm)
LQFP208
(28 x 28 mm)
TFBGA100
(8 x 8 mm)
(1)
TFBGA240+25
(14 x 14 mm)
UFBGA169
(7 x 7 mm)
UFBGA176+25
(10 x 10 mm)
– D2: communication peripherals and timers
– D3: reset/clock control/power management
1.62 to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
Dedicated USB power embedding a 3.3 V
internal regulator to supply the internal PHYs
Embedded regulator (LDO) with configurable
scalable output to supply the digital circuitry
Voltage scaling in Run and Stop mode (6
configurable ranges)
Backup regulator (~0.9 V)
Voltage reference for analog peripheral/V
REF+
Low-power modes: Sleep, Stop, Standby and
V
BAT
supporting battery charging
Memories
Up to 2 Mbytes of Flash memory with read-
while-write support
Up to 1 Mbyte of RAM: 192 Kbytes of TCM
RAM (inc. 64 Kbytes of ITCM RAM +
128 Kbytes of DTCM RAM for time critical
routines), Up to 864 Kbytes of user SRAM, and
4 Kbytes of SRAM in Backup domain
Dual mode Quad-SPI memory interface
running up to 133 MHz
Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND Flash
memory clocked up to 100 MHz in
Synchronous mode
CRC calculation unit
Low-power consumption
V
BAT
battery operating mode with charging
capability
CPU and domain power state monitoring pins
2.95 µA in Standby mode (Backup SRAM OFF,
RTC/LSE ON)
Security
ROP, PC-ROP, active tamper
General-purpose input/outputs
Up to 168 I/O ports with interrupt capability
Clock management
Internal oscillators: 64 MHz HSI, 48 MHz
HSI48, 4 MHz CSI, 32 kHz LSI
External oscillators: 4-48 MHz HSE,
32.768 kHz LSE
Reset and power management
3 separate power domains which can be
independently clock-gated or switched off:
– D1: high-performance capabilities
April 2021
This is information on a product in full production.
DS12110 Rev 8
1/357
www.st.com
STM32H742xI/G STM32H743xI/G
3× PLLs (1 for the system clock, 2 for kernel
clocks) with Fractional mode
Graphics
LCD-TFT controller up to XGA resolution
Chrom-ART graphical hardware Accelerator
(DMA2D) to reduce CPU load
Hardware JPEG Codec
Interconnect matrix
3 bus matrices (1 AXI and 2 AHB)
Bridges (5× AHB2-APB, 2× AXI2-AHB)
4 DMA controllers to unload the CPU
1× high-speed master direct memory access
controller (MDMA) with linked list support
2× dual-port DMAs with FIFO
1× basic DMA with request router capabilities
Up to 22 timers and watchdogs
1× high-resolution timer (2.1 ns max
resolution)
2× 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input (up to 240 MHz)
2× 16-bit advanced motor control timers (up to
240 MHz)
10× 16-bit general-purpose timers (up to
240 MHz)
5× 16-bit low-power timers (up to 240 MHz)
2× watchdogs (independent and window)
1× SysTick timer
RTC with sub-second accuracy and hardware
calendar
Up to 35 communication peripherals
4× I2Cs FM+ interfaces (SMBus/PMBus)
4× USARTs/4x UARTs (ISO7816 interface,
LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
6× SPIs, 3 with muxed duplex I2S audio class
accuracy via internal audio PLL or external
clock, 1x I2S in LP domain (up to 150 MHz)
4x SAIs (serial audio interface)
SPDIFRX interface
SWPMI single-wire protocol master I/F
MDIO Slave interface
2× SD/SDIO/MMC interfaces (up to 125 MHz)
2× CAN controllers: 2 with CAN FD, 1 with
time-triggered CAN (TT-CAN)
2× USB OTG interfaces (1FS, 1HS/FS) crystal-
less solution with LPM and BCD
Ethernet MAC interface with DMA controller
HDMI-CEC
8- to 14-bit camera interface (up to 80 MHz)
Debug mode
SWD & JTAG interfaces
4-Kbyte Embedded Trace Buffer
True random number generators (3
oscillators each)
96-bit unique ID
All packages are ECOPACK2 compliant
Table 1. Device summary
Reference
Part number
11 analog peripherals
3× ADCs with 16-bit max. resolution (up to 36
channels, up to 3.6 MSPS)
1× temperature sensor
2× 12-bit D/A converters (1 MHz)
2× ultra-low-power comparators
2× operational amplifiers (7.3 MHz bandwidth)
1× digital filters for sigma delta modulator
(DFSDM) with 8 channels/4 filters
STM32H742VI, STM32H742ZI,
STM32H742II, STM32H742BI,
STM32H742XI, STM32H742AI,
STM32H742xI/G
STM32H742VG, STM32H742ZG,
STM32H742IG, STM32H742BG,
STM32H742XG, STM32H742AG
STM32H743VI, STM32H743ZI,
STM32H743II, STM32H743BI,
STM32H743XI, STM32H743AI,
STM32H743xI/G
STM32H743VG, STM32H743ZG,
STM32H743IG, STM32H743BG,
STM32H743XG, STM32H743AG
2/357
DS12110 Rev 8
STM32H742xI/G STM32H743xI/G
Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1
3.2
3.3
Arm
®
Cortex
®
-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.1
3.3.2
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4
3.5
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.1
3.5.2
3.5.3
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.6
3.7
Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.7.1
3.7.2
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 35
Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 35
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 35
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 36
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
V
BAT
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Contents
STM32H742xI/G STM32H743xI/G
3.21
3.22
3.23
3.24
3.25
3.26
3.27
3.28
Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 39
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.28.1
3.28.2
3.28.3
3.28.4
3.28.5
3.28.6
3.28.7
3.28.8
High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 44
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 45
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.29
3.30
3.31
3.32
3.33
3.34
3.35
3.36
3.37
3.38
3.39
3.40
3.41
3.42
3.43
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 46
Inter-integrated circuit interface (I
2
C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Universal synchronous/asynchronous receiver transmitter (USART) . . . 47
Low-power universal asynchronous receiver transmitter (LPUART) . . . . 48
Serial peripheral interfaces (SPI)/integrated interchip
sound interfaces (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 50
Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 50
Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 51
SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 51
Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 51
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 52
Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 52
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4
4/357
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DS12110 Rev 8
STM32H742xI/G STM32H743xI/G
Contents
5
6
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Electrical characteristics (rev Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
6.3.14
6.3.15
6.3.16
6.3.17
6.3.18
6.3.19
6.3.20
6.3.21
6.3.22
6.3.23
6.3.24
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 109
Embedded reset and power control block characteristics . . . . . . . . . . 110
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 125
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 130
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 137
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 178
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Temperature and V
BAT
monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
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