Si4421 Universal ISM Band
FSK Transceiver
DESCRIPTION
Silicon Labs’ Si4421 is a single chip, low power, multi-channel FSK
transceiver designed for use in applications requiring FCC or ETSI
conformance for unlicensed use in the 433, 868 and 915 MHz bands.
The Si4421 transceiver is a part of Silicon Labs’ EZRadio
TM
product
line, which produces a flexible, low cost, and highly integrated solution
that does not require production alignments. The chip is a complete
analog RF and baseband transceiver including a multi-band PLL
synthesizer with PA, LNA, I/Q down converter mixers, baseband filters
and amplifiers, and an I/Q demodulator. All required RF functions are
integrated. Only an external crystal and bypass filtering are needed for
operation.
The Si4421 features a completely integrated PLL for easy RF design,
and its rapid settling time allows for fast frequency-hopping, bypassing
multipath fading and interference to achieve robust wireless links. The
PLL’s high resolution allows the usage of multiple channels in any of
the bands. The receiver baseband bandwidth (BW) is programmable to
accommodate various deviation, data rate and crystal tolerance
requirements. The transceiver employs the Zero-IF approach with I/Q
demodulation. Consequently, no external components (except crystal
and decoupling) are needed in most applications.
The Si4421 dramatically reduces the load on the microcontroller with
the integrated digital data processing features: data filtering, clock
recovery, data pattern recognition, integrated FIFO and TX data
register. The automatic frequency control (AFC) feature allows the use
of a low accuracy (low cost) crystal. To minimize the system cost, the
Si4421 can provide a clock signal for the microcontroller, avoiding the
need for two crystals.
For low power applications, the Si4421 supports low duty cycle
operation based on the internal wake-up timer.
Si4421
PIN ASSIGNMENT
SDI
SCK
nSEL
SDO
nIRQ
FSK / DATA / nFFS
DCLK / CFIL / FFIT
CLK
nINT / VDI
ARSSI
VDD
RF1
RF2
VSS
nRES
XTL / REF
This document refers to Si4421-IC rev A1.
See www.silabs.com/integration for any applicable errata.
See back page for ordering information.
FEATURES
Fully integrated (low BOM, easy design-in)
No alignment required in production
Fast-settling, programmable, high-resolution PLL synthesizer
Fast frequency-hopping capability
High bit rate (up to 115.2 kbps in digital mode and 256 kbps
in analog mode)
Direct differential antenna input/output
Integrated power amplifier
Programmable TX frequency deviation (15 to 240 kHz)
Programmable RX baseband bandwidth (67 to 400 kHz)
Analog and digital RSSI outputs
Automatic frequency control (AFC)
Data quality detection (DQD)
Internal data filtering and clock recovery
RX synchron pattern recognition
SPI compatible serial control interface
Clock and reset signals for microcontroller
16-bit RX Data FIFO
Two 8-bit TX data registers
Low power duty cycle mode
Standard 10 MHz crystal reference with on-chip tuning
Wake-up timer
2.2 to 3.8 V supply voltage
Low power consumption
Low standby current (0.3
A)
Compact 16 pin TSSOP package
Supports very short packets (down to 3 bytes)
Excellent temperature stability of the RF parameters
Good adjacent channel rejection/blocking
FUNCTIONAL BLOCK DIAGRAM
MIX
I
AMP
OC
clk
LNA
RF2 12
MIX
Q
Self cal.
I/Q
DEMOD
Data Filt
CLK Rec
data
6
7
DCLK /
CFIL /
FFIT /
FSK /
DATA /
nFFS
RF1 13
AMP
OC
FIFO
PA
PLL & I/Q VCO
with cal.
RF Parts
BB Amp/Filt./Limiter
RSSI
COMP
DQD
AFC
Data processing units
CLK div
Xosc
WTM
with cal.
TYPICAL APPLICATIONS
LBD
Low Power parts
Controller
Bias
15
ARSSI
1
SDI
2
SCK
3
4
5
nIRQ
10
nRES
16
nINT /
VDI
11
VSS
14
VDD
8
CLK
9
XTL /
REF
nSEL SDO
Home security and alarm
Remote control, keyless entry
Wireless keyboard/mouse and other PC peripherals
Toy controls
Remote keyless entry
Tire pressure monitoring
Telemetry
Personal/patient data logging
Remote automatic meter reading
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Si4421-DS rev 2.4r 0708
www.silabs.com
Si4421
2
Si4421
DETAILED FEATURE-LEVEL DESCRIPTION
The Si4421 FSK transceiver is designed to cover the unlicensed
frequency bands at 433, 868 and 915 MHz. The device
facilitates compliance with FCC and ETSI requirements.
The receiver block employs the Zero-IF approach with I/Q
demodulation, allowing the use of a minimal number of external
components in a typical application. The Si4421 incorporates a
fully integrated multi-band PLL synthesizer, PA with antenna
tuning, an LNA with switchable gain, I/Q down converter mixers,
baseband filters and amplifiers, and an I/Q demodulator
followed by a data filter.
40.0
20.0
0.00
Full Baseband Amplifier Transfer Function
BW=67kHz
Output level (dB)
-20.0
-40.0
-60.0
-80.0
-100
-120
-140
100
PLL
The programmable PLL synthesizer determines the operating
frequency, while preserving accuracy based on the on-chip crystal-
controlled reference oscillator. The PLL’s high resolution allows the
usage of multiple channels in any of the bands.
1k
10k
Frequency (Hz)
100k
1M
Data Filtering and Clock Recovery
Output data filtering can be completed by an external capacitor
or by using digital filtering according to the final application.
Analog operation:
The filter is an RC type low-pass filter followed
by a Schmitt-trigger (St). The resistor (10 kOhm) and the St are
integrated on the chip. An (external) capacitor can be chosen
according to the actual bit rate. In this mode, the receiver can
handle up to 256 kbps data rate. The FIFO cannot be used in this
mode and clock is not provided for the demodulated data.
Digital operation:
A digital filter is used with a clock frequency at
29 times the bit rate. In this mode, there is a clock recovery
circuit (CR), which can provide synchronized clock to the data.
Using this clock the received data can fill a FIFO. The CR has
three operation modes: fast, slow, and automatic. In slow mode,
its noise immunity is very high, but it has slower settling time and
requires more accurate data timing than in fast mode. In
automatic mode, the CR automatically changes between fast and
slow mode. The CR starts in fast mode, then after locking, it
automatically switches to slow mode
(Only the digital data filter and the clock recovery use the bit rate
clock. For analog operation, there is no need for setting the
correct bit rate.)
RF Power Amplifier (PA)
The power amplifier has an open-collector differential output and
can directly drive different PCB antennas with a programmable
output power level. An automatic antenna tuning circuit is built in
to avoid costly trimming procedures and the so-called “hand
effect”.
LNA
The LNA has approximately 250 Ohm input impedance, which
functions well with the proposed antennas (see: Application
Notes available from
www.silabs.com/integration)
If the RF input of the chip is connected to 50 Ohm devices, an
external matching circuit is required to provide the correct
matching and to minimize the noise figure of the receiver.
The LNA gain can be selected in four steps (between 0 and
-20dB relative to the highest gain) according to RF signal
strength. It can be useful in an environment with strong
interferers.
Baseband Filters
The receiver bandwidth is selectable by programming the
bandwidth (BW) of the baseband filters. This allows setting up
the receiver according to the characteristics of the signal to be
received.
An appropriate bandwidth can be chosen to accommodate
various FSK deviation, data rate and crystal tolerance
requirements. The filter structure is 7
th
order Butterworth low-
pass with 40 dB suppression at 2 · BW frequency. Offset
cancellation is done by using a high-pass filter with a cut-off
frequency below 7 kHz.
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Si4421
Data Validity Blocks
RSSI
A digital RSSI output is provided to monitor the input signal level.
It goes high if the received signal strength exceeds a given
preprogrammed level. An analog RSSI signal is also available.
The RSSI settling time depends on the external filter capacitor.
Pin 15 is used as analog RSSI output. The digital RSSI can be
monitored by reading the status register.
suggested to turn the output buffer off by the
Power
Management Command
(page 16).
Low Battery Voltage Detector
The low battery detector circuit monitors the supply voltage and
generates an interrupt if it falls below a programmable threshold
level. The detector circuit has 50 mV hysteresis.
Wake-Up Timer
The wake-up timer has very low current consumption (1.5 µA
typical) and can be programmed from 1 ms to several days with
an accuracy of ±10%.
The wake-up timer calibrates itself to the crystal oscillator at
every startup. For proper calibration of the wake-up timer the
crystal oscillator must be running before the wake-up timer is
enabled. The calibration process takes approximately 0.5ms.
For the crystal start up time (tsx), see page 12.
Typical Analog ARSSI Voltage vs. RF Input Power
ARSSI voltage [mV]
1150
450
Event Handling
-100
Input Power [dBm]
-65
DQD
The operation of the Data Quality Detector is based on counting
the spikes on the unfiltered received data. High output signal
indicates an operating FSK transmitter within baseband filter
bandwidth from the local oscillator. DQD threshold parameter
can be set by using the
Data Filter Command
(page 20).
In order to minimize current consumption, the transceiver
supports different power saving modes. Active mode can be
initiated by several wake-up events (negative logical pulse on
nINT input, wake-up timer timeout, low supply voltage detection,
on-chip FIFO filled up or receiving a request through the serial
interface).
If any wake-up event occurs, the wake-up logic generates an
interrupt signal, which can be used to wake up the
microcontroller,
effectively
reducing
the
period
the
microcontroller has to be active. The source of the interrupt can
be read out from the transceiver by the microcontroller through
the SDO pin.
AFC
By using an integrated Automatic Frequency Control (AFC)
feature, the receiver can minimize the TX/RX offset in discrete
steps, allowing the use of:
Interface and Controller
An SPI compatible serial interface lets the user select the
frequency band, center frequency of the synthesizer, and the
bandwidth of the baseband signal path. Division ratio for the
microcontroller clock, wake-up timer period, and low supply
voltage detector threshold are also programmable. Any of these
auxiliary functions can be disabled when not needed. All
parameters are set to default after power-on; the programmed
values are retained during sleep mode. The interface supports
the read-out of a status register, providing detailed information
about the status of the transceiver and the received data.
The transmitter block is equipped with two 8-bit wide TX data
registers. It is possible to write 8 bits into the register in burst
mode and the internal bit rate generator transmits the bits out
with the predefined rate. For further details, see the
TX Register
Buffered Data Transmission
section (page 29).
It is also possible to store the received data bits into a FIFO
register and read them out in a buffered mode.
Narrower receiver bandwidth (i.e. increased
sensitivity)
Higher data rate
Inexpensive crystals
Crystal Oscillator
The Si4421 has a single-pin crystal oscillator circuit, which
provides a 10 MHz reference signal for the PLL. To reduce
external parts and simplify design, the crystal load capacitor is
internal and programmable. Guidelines for selecting the
appropriate crystal can be found later in this datasheet.
The transceiver can supply a clock signal for the microcontroller;
so accurate timing is possible without the need for a second
crystal.
When the microcontroller turns the crystal oscillator off by
clearing the appropriate bit using the
Power Management
Command
(page 16), the chip provides a fixed number (192) of
further clock pulses (“clock tail”) for the microcontroller to let it
go to idle or sleep mode. If this clock output is not used, it is
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Si4421
PACKAGE PIN DEFINITIONS
Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output
SDI
SCK
nSEL
SDO
nIRQ
FSK / DATA / nFFS
DCLK / CFIL / FFIT
CLK
nINT / VDI
ARSSI
VDD
RF1
RF2
VSS
nRES
XTL / REF
Pin
1
2
3
4
5
Name
SDI
SCK
nSEL
SDO
nIRQ
FSK
DATA
nFFS
DLCK
Type
DI
DI
DI
DO
DO
DI
DO
DI
DO
AIO
DO
DO
AIO
AIO
DIO
S
AIO
AIO
S
AO
DI
DO
Function
Data input of the serial control interface
Clock input of the serial control interface
Chip select input of the serial control interface (active low)
Serial data output with bus hold
Interrupt request output (active low)
Transmit FSK data input (internal pull up resistor 133 k)
Received data output (FIFO not used)
FIFO select input (active low). In FIFO mode, when bit
ef
is set in
Configuration Setting Command,
page 16 (internal pull up resistor 133 k)
Received data clock output (Digital filter used, FIFO not used)
External data filter capacitor connection (Analog filter used)
FIFO interrupt (active high). In FIFO mode, when bit
ef
is set in
Configuration Setting Command
Microcontroller clock output
Crystal connection (the other terminal of crystal to VSS) or external reference input
External reference input. Use 33 pF series coupling capacitor
Open drain reset output with internal pull-up and input buffer (active low)
Ground reference voltage
RF differential signal input/output
RF differential signal input/output
Positive supply voltage
Analog RSSI output
Interrupt input (active low)
Valid data indicator output
6
7
8
9
10
11
12
13
14
15
16
CFIL
FFIT
CLK
XTL
REF
nRES
VSS
RF2
RF1
VDD
ARSSI
nINT
VDI
Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O settings of the transceiver.
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