AN414
EZR
ADIO
P R O
®
L
AYOUT
D
ESIGN
G
UIDE
1. Introduction
The purpose of this application note is to help users design EZRadioPRO
®
PCBs using design practices that allow
for good RF performance. This application note also help designers by separating TX and RX concerns.
The RF performance and the critical maximum peak voltage on the output pin strongly depend on the PCB layout
as well as the design of the matching networks. For optimal performance, Silicon Labs recommends the use of the
PCB layout design hints described in the following sections.
2. Design Recommendations when Using EZRadioPRO RF ICs
Extensive testing has been completed using reference designs provided by Silicon Labs. It is recommended to
designers to use the reference designs “as-is” since they minimize detuning effects caused by parasitics,
component placement, and PCB routing.
When layouts cannot be followed as shown by the reference designs (due to PCB size and shape limitations),
the following layout design rules are recommended.
2.1. Guidelines for Layout Design when Using the Si4430/31
The Si4430/31 devices use a Class-E type TX matching network with a typical output power level of +13 dBm at
VDD = 3.3 V. Two basic types of board layout configurations exist at all frequency bands: the Split TX/RX type and
the Direct Tie type. In the Split TX/RX type, the TX and RX paths are separated, and individual SMA connectors are
provided for each path. In the Direct Tie type, the TX and RX paths are connected together directly, without any
additional RF switch. The operating principle of both types and the reference designs with element values are
given in “AN436: Si4030/4031/4430/4431 PA Matching” for wirewound and multilayer type 0402 size SMD
inductances as well.
The Split and Direct Tie type boards have slightly different PCB layouts, which are described in separate sections.
2.1.1. Split Type Matching Network Layout Based upon the 4431-T-B1_B Test Card
(Separate TX and RX Paths with Two Antennas)
Examples shown in this section of the guide are based upon the layout of the 4431-T-B1_B test cards. These cards
contain two separate antennas for the TX and RX paths. This type of test card is best suited for demonstrating the
output power and sensitivity of the EZRadioPRO RFICs. For this purpose, the TX and RX path layouts are
separated and isolated as much as possible to minimize the mutual coupling effects. This type of test card is
recommended for laboratory evaluation and not for range tests because the presence of two closely-spaced
antennas may cause “shadowing” when receiving a radiated signal.
The main layout design concepts are reviewed through this layout to demonstrate the basic principles. However,
for an actual application, the layouts of the test cards with a single antenna (or with antenna diversity) should be
used as references. The schematic of the Split type matching network for Si4431 RevB1 is shown in Figure 1.
Rev. 0.2 12/10
Copyright © 2010 by Silicon Laboratories
AN414
AN414
Figure 1. Schematic of the Split Type Matching Network for the Si4431 RevB1
The layout structure of the Split type matching network is shown in Figure 2.
2
Rev. 0.2
AN414
Ground
TX Section
Metallization
RX Section
V
DD
Filter Capacitors
PCB Vias
Crystal
RF IC
Figure 2. Split Type Matching Network Layout Structure
2.1.2. Layout Design Guidelines
The choke inductor (LC) should be placed as close to the TX pin of the RF IC as possible (even if this means
the RX is further away).
The parallel inductor in the RX path (LR) should be perpendicular to the choke inductor (LC) in the TX path
because this will reduce TX-to-RX coupling.
The TX and RX sections should be separated by a GND metal on the top layer to reduce coupling.
The neighboring matching network components should be placed as close to each other as possible in order to
minimize any PCB parasitic capacitance to ground and the series parasitic inductances between the
components.
Increase the grounding effect in the thermal straps used with capacitors. In addition, thicken the trace near the
GND pin of these capacitors. This will minimize series parasitic inductance between the ground pour and the
GND pins. Additional vias placed close to the GND pin of capacitors (thus connecting it to the bottom layer GND
plane) will further help reduce these effects.
Figure 3 illustrates the positioning and orientation of the LC and LR components, the separating GND metal
between the TX and RX sections, and thermal strapping on the shunt capacitors.
Rev. 0.2
3
AN414
Thermal PCB Straps on Capacitors
GND Metal between
the TX and RX Sides
Nearby inductors of the TX path should be kept perpendicular to each other to reduce coupling between stages
of the low-pass filter and match. This helps to improve filter attenuation at higher harmonic frequencies.
Use at least 0.5 mm separation between traces/pads to the adjacent GND pour in the areas of the matching
networks. This minimizes the parasitic capacitance and reduces detuning effects.
Figure 4 illustrates the orientation of the inductors of the TX path and the separation of the matching network
traces/pads from the GND metal.
Thermal PCB Straps on Capacitors
LR
LC
TX Pin
Figure 3. Si4331 Component Orientation, Placement, and GND Metallization
4
Rev. 0.2
AN414
The smaller VDD bypass capacitors (C1 = 33 pF and C2 = 100 pF) should be kept as close to the VDD pin as
possible.
The exposed pad footprint for the paddle of the RF IC should use as many vias as possible to ensure good
grounding and heatsink capability. In the reference designs, there are nine vias, each with 12 mil diameter. The
paddle ground should also be connected to the top layer GND metal (if possible) to further improve RF
grounding; this may be accomplished with diagonal trace connections through the corners of the RFIC footprint.
The crystal should be placed as close as possible to the RFIC to ensure that wire parasitic capacitances are
kept as low as possible; this reduces any frequency offsets that may occur.
Place ground metal between the crystal and the VDD trace to reduce coupling effects.
Figure 5 illustrates the grounding of the RFIC, the crystal, and VDD filter capacitor positions, and the isolating
ground metal between the VDD trace and the crystal.
Separation of Traces from GND
Rev. 0.2
LM2
LM
L0
LC
Figure 4. TX Side Inductor Orientation, Thermal Strapping, and Separation from GND
5
