Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1 Mrad(Si)
- Latchup immune (LET > 100 MeV-cm
2
/mg)
Packaging options:
- 48-lead flatpack
Standard Microcircuit Drawing 5962-01535
- QML Q and V compliant part
Compatible with TIA/EIA-644 LVDS standard
INTRODUCTION
The UT54LVDS218 Deserializer converts the three LVDS data
streams back into 21 bits of CMOS/TTL data. At a transmit clock
frequency of 75MHz, 21 bits of TTL data are transmitted at a
rate of 525Mbps per LVDS data channel. Using a 75MHz clock,
the data throughput is 1.575 Gbit/s (197 Mbytes/sec).
The UT54LVDS218 Deserializer allows the use of wide, high
speed TTL interfaces while reducing overall EMI and cable size.
All pins have Cold Spare buffers. These buffers will be high
impedance when V
DD
is tied to V
SS
.
LVDS TO-PARALLEL TTL
DATA (LVDS)
21
CMOS/TTL OUTPUTS
CLOCK (LVDS)
PLL
RECEIVER CLOCK OUT
POWER DOWN
Figure 1. UT54LVDS218 Deserializer Block Diagram
1
RxOUT 17
RxOUT 18
GND
RxOUT 19
RxOUT 20
N/C
LVDS GND
RxIN0-
RxIN0+
RxIN1-
RxIN1+
LVDS V
DD
LVDS GND
RxIN2-
RxIN2+
RxCLK IN-
RxCLK IN+
LVDS GND
PLL GND
PLL V
DD
PLL GND
PWR DWN
RxCLK OUT
RxOUT0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
UT54LVDS218
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
DD
RxOUT 16
RxOUT 15
RxOUT 14
GND
RxOUT 13
V
DD
RxOUT 12
RxOUT 11
RxOUT 10
GND
RxOUT 9
V
DD
RxOUT 8
RxOUT 7
RxOUT 6
GND
RxOUT 5
RxOUT 4
RxOUT 3
V
DD
RxOUT 2
RxOUT 1
GND
PIN DESCRIPTION
Pin Name
RxIN+
RxIN-
RxOUT
RxCLK IN+
RxCLK IN-
RxCLK OUT
PWR DWN
V
DD
GND
PLL V
DD
PLL GND
LVDS V
DD
LVDS GND
I/O
I
I
O
I
I
O
I
I
I
I
I
I
I
No.
3
3
21
1
1
1
1
4
5
1
2
1
3
Description
Positive LVDS differential data inputs
1
Negative LVDS differential data output
1
TTL level data outputs
Positive LVDS differential clock input
Negative LVDS differential clock input
TTL level clock output. The rising edge acts
as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input)
the receiver outputs are low
Power supply pins for TTL outputs and log-
ic
Ground pins for TTL outputs and logic
Power supply for PLL
Ground pin for PLL
Power supply pin for LVDS pins
Ground pins for LVDS inputs
Figure 2. UT54LVDS218 Pinout
TX
TxIN
0
1
2
Notes:
1. These receivers have input fail-safe bias circuitry to guarantee a stable receiver
output for floating or terminated receiver inputs. Under these conditions receiver
inputs will be in a HIGH state. If a clock signal is present, data outputs will all
be HIGH; if the clock input is also floating/terminated outputs will remain in
the last valid state. A floating/terminated clock input will result in a LOW clock
output.
LVDS CABLE
MEDIA DEPENDENT DATA
(LVDS)
RX
RxOUT
0
1
2
CMOS/
TTL
18
19
20
18
19
20
TxCLK
CLOCK
(LVDS)
RxCLK
GND
PCB
SHIELD
Figure 3. UT54LVDS218 Typical Application
PCB
2
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.3 to 4.0V
-0.3 to (V
DD
+ 0.3V)
-65 to +150°C
1.25 W
+150°C
10°C/W
±
10mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
4. For cold spare mode (V
DD
= V
SS
), V
I/O
may be -0.3V to the maximum recommended operating V
DD
+0.3V.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage
LIMITS
3.0 to 3.6V
-55 to +125°C
0V to V
DD
3
DC ELECTRICAL CHARACTERISTICS
1
SYMBOL
PARAMETER
(V
DD
= 3.0V to 0.3V; -55°C < T
C
< +125°C)
CONDITION
MIN
MAX
UNIT
CMOS/TTL DC SPECIFICATIONS (PWR DWN, RXOUT)
V
IH
V
IL
V
OL
V
OH
I
IH
I
IL
V
CL
I
CS
I
OS2, 3
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level output voltage
High-level input current
Low-level input current
Input clamp voltage
Cold spare leakage current
Output short circuit current
I
OL
= 2mA
I
OL
= -0.4mA
V
IN
=3.6V; V
DD
= 3.6V
V
IN
=0V; V
DD
= 3.6V
I
CL
= -18mA
V
IN
=3.6V; V
DD
= V
SS
V
OUT
= 0V
-20
-15
2.7
-10
-10
+10
+10
-1.5
+20
-130
2.0
GND
V
DD
0.8
0.3
V
V
V
V
µA
µA
V
µA
mA
LVDS RECEIVER DC SPECIFICATIONS (IN+, IN-)
V
ΤΗ3
V
ΤL3
V
CMR
I
IN
Differential input high threshold
Differential input low threshold
Common mode voltage range
Input current
V
CM
= +1.2V
V
CM
= +1.2V
V
ID
=210mV
V
IN
= +2.4V, V
DD
= 3.6V
V
IN
= 0V, V
DD
= 3.6V
I
CSIN
Cold spare leakage current
V
IN
= 3.6V, V
DD
= V
SS
-100
0.2
-10
-10
-20
2.00
+10
+10
+20
+100
mV
mV
V
µA
µA
µA
Supply Current
I
CC3
I
CCPD
Active supply current
Power down supply current
CL=8pF (see Figure 4)
PWR DWN = Low, LVDS inputs =
logic low
105
2.0
mΑ
mA
Notes:
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground.
2. Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time for a maximum
duration of one second.
3. Guaranteed by characterization.
4
RECEIVER SWITCHING CHARACTERISTICS
1
(V
DD
= 3.0V to 3.6V; TA = -55°C to +125°C)
SYMBOL
CLHT
3
CHLT
3
RSPos0
3
RSPos1
3
RSPos2
3
RSPos3
3
RSPos4
3
RSPos5
3
RSPos6
3
RCOP
3
RCOH
3
RCOL
3
RSRC
4
RHRC
4
RCCD
2
RRLLS
RPDD
PARAMETER
CMOS/TTL Low-to-High Transition Time (Figure 5)
CMOS/TTL High-to-Low Transition Time (Figure 5)
Receiver Input Strobe Position for Bit 0 (Figure 10)
Receiver Input Strobe Position for Bit 1 (Figure 10)
Receiver Input Strobe Position for Bit 2 (Figure 10)
Receiver Input Strobe Position for Bit 3 (Figure 10)
Receiver Input Strobe Position for Bit 4 (Figure 10)
Receiver Input Strobe Position for Bit 5 (Figure 10)
Receiver Input Strobe Position for Bit 6(Figure 10)
RxCLK OUT Period (Figure 6)
RxCLK OUT High Time (Figure 6)
RxCLK OUT Low Time (Figure 6)
RxOUT Setup to RxCLK OUT (Figure 6)
RxOUT Hold to RxCLK OUT (Figure 6)
RxCLK IN to RxCLK OUT Delay (Figure 7)
Receiver Phase Lock Loop Set (Figure 8)
Receiver Powerdown Delay (Figure 9)
f=75MHz
f=75MHz
f=75MHz
f=75MHz
f=75MHz
f=75MHz
f=75MHz
f=75MHz
f=75MHz
f=75MHz
f=75MHz
f=75MHz
f=75MHz
0.50
2.41
4.31
6.22
8.12
10.03
11.93
13.3
3.6
3.6
3.5
3.5
3.4
8.3
10
2
MIN
MAX
3.5
3.5
1.24
3.15
5.05
6.96
8.86
10.77
12.67
66.7
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
Notes:
1. Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and
max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference (both
dependent on type/length of cable), and source clock jitter less than 250 ps (calculated from T
POS
- R
POS
) - see Figure 11.
2. Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for
LVDS217 Serializer and the LVDS218 Deserializer is (T + TCCD) + 2*T + RCCD), where T = Clock period.
