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74HC08M/TR

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74HC08
High-Speed CMOS Logic
Quad 2-Input AND Gate
[ /Title
(CD54H
C08,
CD54H
CT08,
CD74H
C08,
CD74H
CT08)
/Sub-
ject
(High
Features
• Buffered Inputs
• Typical Propagation Delay: 7ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
• CMOS Input Compatibility, I
l
1µA at V
OL
, V
OH
PART NUMBER
CD54HC08F3A
CD54HCT08F3A
CD74HC08E
CD74HC08M
CD74HC08MT
CD74HC08M96
CD74HC08PW
CD74HC08PWR
CD74HCT08E
CD74HCT08M
CD74HCT08MT
CD74HCT08M96
Description
The
CD54HC08,
CD54HCT08,
CD74HC08,
and
CD74HCT08 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The 74HCT logic family is functionally pin
compatible with the standard 74LS logic family.
Ordering Information
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld TSSOP
14 Ld TSSOP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
HTTP://WWW.HGSEMI.NET
1
2015 AUG
74HC08
Pinout
CD74HCT08
(PDIP, SOIC)
TOP VIEW
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
GND
2B
2Y
1Y
2A
Functional Diagram
1
1A
2
1B
3
4
5
6
7
12
4A
11
4Y
10
3B
9
3A
8
3Y
13
4B
14
V
CC
TRUTH TABLE
INPUTS
nA
L
L
H
H
nB
L
H
L
H
OUTPUT
nY
L
L
L
H
H = High Voltage Level, L = Low Voltage Level
HC Logic Symbol
HCT Logic Symbol
nA
nA
nB
nY
nB
nY
HTTP://WWW.HGSEMI.NET
2
2015 AUG
74HC08
Absolute Maximum Ratings
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC or
I
GND
. . . . . . . . . . . . . . . . . .±50mA
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Maximum Junction Temperature (Hermetic Package or Die) . . . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
4.5
6
Low Level Input
Voltage
V
IL
-
-
2
4.5
6
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
I
V
CC
or
GND
V
OL
V
IH
or
V
IL
V
OH
V
IH
or
V
IL
-0.02
-0.02
-0.02
-
-4
-5.2
0.02
0.02
0.02
-
4
5.2
-
2
4.5
6
-
4.5
6
2
4.5
6
-
4.5
6
6
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.98
5.48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.26
0.26
±0.1
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.84
5.34
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.33
0.33
±1
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.7
5.2
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.4
0.4
±1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
SYMBOL
V
I
(V)
I
O
(mA) V
CC
(V)
MIN
25
o
C
TYP
MAX
-40
o
C TO 85
o
C
MIN
MAX
-55
o
C TO 125
o
C
MIN
MAX
UNITS
HTTP://WWW.HGSEMI.NET
3
2015 AUG
74HC08
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Quiescent Device
Current
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
I
I
V
CC
and
GND
V
CC
or
GND
V
CC
- 2.1
V
OL
V
IH
or
V
IL
V
IH
V
IL
V
OH
-
-
V
IH
or
V
IL
-
-
-0.02
4.5 to
5.5
4.5 to
5.5
4.5
2
-
4.4
-
-
-
-
0.8
-
2
-
4.4
-
0.8
-
2
-
4.4
-
0.8
-
V
V
V
SYMBOL
I
CC
V
I
(V)
V
CC
or
GND
I
O
(mA) V
CC
(V)
0
6
MIN
-
25
o
C
TYP
-
MAX
2
-40
o
C TO 85
o
C
MIN
-
MAX
20
-55
o
C TO 125
o
C
MIN
-
MAX
40
UNITS
µA
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0
5.5
-
±0.1
-
±1
-
±1
µA
I
CC
∆I
CC
(Note 2)
0
-
5.5
4.5 to
5.5
-
-
-
100
2
360
-
-
20
450
-
-
40
490
µA
µA
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
HC TYPES
Propagation Delay,
Input to Output (Figure 1)
t
PLH
, t
PHL
C
L
= 50pF
2
4.5
6
Propagation Delay, Data Input to
Output Y
t
PLH
, t
PHL
C
L
= 15pF
5
-
-
-
-
-
-
-
7
90
18
15
-
-
-
-
-
115
23
20
-
-
-
-
-
135
27
23
-
ns
ns
ns
ns
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
MIN
TYP
MAX
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
MAX
MIN
MAX
UNITS
HTTP://WWW.HGSEMI.NET
4
2015 AUG
74HC08
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
Transition Times (Figure 1)
SYMBOL
t
TLH
, t
THL
(Continued)
V
CC
(V)
2
4.5
6
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
HCT TYPES
Propagation Delay, Input to
Output Y (Figure 2)
Propagation Delay, Data Input to
Output Y
Transition Times (Figure 2)
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
NOTES:
3. C
PD
is used to determine the dynamic power consumption, per gate.
4. P
D
= V
CC2
f
i
(C
PD
+ C
L
) where f
i
= input frequency, C
L
= output load capacitance, V
CC
= supply voltage.
t
PLH
, t
PHL
t
PLH
, t
PHL
t
TLH
, t
THL
C
I
C
PD
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
C
L
= 50pF
-
4.5
5
4.5
-
5
-
-
-
-
-
-
10
-
-
51
25
-
15
10
-
-
-
-
-
-
31
-
19
10
-
-
-
-
-
-
38
-
22
10
-
ns
ns
ns
pF
pF
C
I
C
PD
-
-
-
5
25
o
C
MIN
-
-
-
-
-
TYP
-
-
-
-
37
MAX
75
15
13
10
-
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
-
-
-
-
-
MAX
95
19
16
10
-
MIN
-
-
-
-
-
MAX
110
22
19
10
-
UNITS
ns
ns
ns
pF
pF
TEST
CONDITIONS
C
L
= 50pF
Test Circuits and Waveforms
t
r
= 6ns
INPUT
90%
50%
10%
t
TLH
90%
50%
10%
t
PHL
t
PLH
t
f
= 6ns
V
CC
INPUT
GND
t
THL
t
r
= 6ns
2.7V
1.3V
0.3V
t
TLH
90%
INVERTING
OUTPUT
t
PHL
t
PLH
1.3V
10%
t
f
= 6ns
3V
GND
t
THL
INVERTING
OUTPUT
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
HTTP://WWW.HGSEMI.NET
5
2015 AUG
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