74HC4052/
74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
1. General description
The 74HC4052; 74HCT4052 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4052B. The device is specified in compliance with JEDEC standard no. 7A.
The 74HC4052; 74HCT4052 is a dual 4-channel analog multiplexer/demultiplexer with
common select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to
nY3) and a common input/output (pin nZ). The common channel select logics include two
digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). When
pin E = LOW, one of the four switches is selected (low-impedance ON-state) with pins S0
and S1. When pin E = HIGH, all switches are in the high-impedance OFF-state,
independent of pins S0 and S1.
V
CC
and GND are the supply voltage pins for the digital control inputs (pins S0, S1 and E).
The V
CC
to GND ranges are 2.0 V to 10.0 V for the 74HC4052 and 4.5 V to 5.5 V for the
74HCT4052. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing between V
CC
as a positive limit and V
EE
as a negative limit. V
CC
−
V
EE
may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is connected to GND (typically
ground).
2. Features
Wide analog input voltage range from
−5
V to +5 V
Low ON resistance:
80
Ω
(typical) at V
CC
−
V
EE
= 4.5 V
70
Ω
(typical) at V
CC
−
V
EE
= 6.0 V
60
Ω
(typical) at V
CC
−
V
EE
= 9.0 V
Logic level translation: to enable 5 V logic to communicate with
±5
V analog signals
Typical ‘break before make’ built-in
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
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74HC4052/
74HCT4052
4. Functional diagram
10
13
1Z
1Y0
10
9
S0
S1
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
6
E
2Z
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0
1
G4
4
×
9
6
12
14
15
11
1
5
2
4
13
3
0
3
MDX
0
1
2
3
1
5
2
4
12
14
15
11
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2Y3
3
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
nYn
V
CC
V
EE
V
CC
V
CC
V
CC
from
logic
V
EE
nZ
V
EE
mnb043
Fig 3.
Schematic diagram (one switch)
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2018 AUG
74HC4052/
74HCT4052
V
DD
16
13
12
1Z
1Y0
14
1Y1
15
S0
10
1Y2
11
9
LOGIC
LEVEL
CONVERSION
1-OF-4
DECODER
1
1Y3
S1
2Y0
E
6
5
2Y1
2
2Y2
4
2Y3
3
8
V
SS
7
V
EE
2Z
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Fig 4.
Functional diagram
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74HC4052/
74HCT4052
5. Pinning information
5.1 Pinning
74HC4052
74HCT4052
2Y0
2Y2
2Z
2Y3
2Y1
E
V
EE
GND
1
2
3
4
5
6
7
8
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74HC4052
74HCT4052
16 V
CC
15 1Y2
2Y2
14 1Y1
13 1Z
12 1Y0
11 1Y3
V
EE
10 S0
9
S1
7
8
GND
S1
9
2Z
2Y3
2Y1
E
2
3
4
5
6
V
CC(1)
terminal 1
index area
16 V
CC
15 1Y2
14 1Y1
13 1Z
12 1Y0
11 1Y3
10 S0
2Y0
1
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Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 5.
Pin configuration for DIP16, SO16 and
(T)SSOP16
Fig 6.
Pin configuration for DHVQFN16
5.2 Pin description
Table 2.
Symbol
2Y0
2Y2
2Z
2Y3
2Y1
E
V
EE
GND
S1
S0
1Y3
1Y0
1Z
1Y1
1Y2
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
independent input or output 2Y0
independent input or output 2Y2
common input or output 2
independent input or output 2Y3
independent input or output 2Y1
enable input (active LOW)
negative supply voltage
ground (0 V)
select logic input 1
select logic input 0
independent input or output 1Y3
independent input or output 1Y0
common input or output 1
independent input or output 1Y1
independent input or output 1Y2
positive supply voltage
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74HC4052/
74HCT4052
6. Functional description
6.1 Function table
Table 3.
Input
E
L
L
L
L
H
[1]
Function table
[1]
Channel on
S1
L
L
H
H
X
S0
L
H
L
H
X
nY0 and nZ
nY1 and nZ
nY2 and nZ
nY3 and nZ
none
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to V
EE
= GND (ground = 0 V).
Symbol
V
CC
I
IK
I
SK
I
SW
I
EE
I
CC
I
GND
T
stg
P
tot
P
[1]
Parameter
supply voltage
input clamping current
switch clamping current
switch current
supply current
supply current
ground current
storage temperature
total power dissipation
power dissipation
Conditions
[1]
Min
−0.5
-
-
-
-
-
-
−65
Max
+11.0
±20
±20
±25
±20
50
−50
+150
500
100
Unit
V
mA
mA
mA
mA
mA
mA
°C
mW
mW
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
SW
<
−0.5
V or V
SW
> V
CC
+ 0.5 V
−0.5
V < V
SW
< V
CC
+ 0.5 V
T
amb
=
−40 °C
to +125
°C
per switch
[2]
-
-
To avoid drawing V
CC
current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the bidirectional switch must
not exceed 0.4 V. If the switch current flows into pins nZ, no V
CC
current will flow out of pins nYn. In this case there is no limit for the
voltage drop across the switch, but the voltages at pins nYn and nZ may not exceed V
CC
or V
EE
.
For DIP16 packages: above 70
°C
the value of P
tot
derates linearly with 12 mW/K.
For SO16 packages: above 70
°C
the value of P
tot
derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60
°C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60
°C
the value of P
tot
derates linearly with 4.5 mW/K.
[2]
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