82551ER Fast Ethernet PCI
Controller
Networking Silicon - 82551ER
Datasheet
Product Features
Enhanced IP Protocol Support
— TCP, UDP, IPv4 checksum offload
— Received checksum verification
Quality of Service (QoS)
— Multiple priority transmit queues
Optimum Integration for Lowest Cost Solution
— Integrated IEEE 802.3 10BASE-T and
100BASE-TX compatible PHY
— 32-bit PCI master interface
— Thin BGA 15mm
2
package
Integrated power management functions
— ACPI and PCI power management standards
compliance
— Wake on “interesting” packets and link status
change support
PHY detects polarity, MDI-X, and cable lengths.
Auto MDI, MDI-X crossover at all speeds
XOR tree mode support
High Performance Networking Functions
— Early release
— 8255x controller family chained memory
structure
— Improved dynamic transmit chaining with
multiple priorities transmit queues
— Full pin compatibility with the 82559 and
82559ER controllers
— Backward compatible software to 82559ER
controllers
— Full duplex support at 10 and 100 Mbps
— IEEE 802.3u auto-negotiation support
— 3 KB transmit and receive FIFOs
— Fast back-to-back transmission support with
minimum interframe spacing
— IEEE 802.3x 100BASE-TX flow control
support
— Adaptive Technology
Low Power Features
— Advanced Power Management (APM)
capabilities
— Low power 3.3 V device
— Efficient dynamic standby mode
— Deep power-down support
— Clockrun protocol support
82551ER Enhancements
— Improved bit error rate performance
— HWI support
— Deep power-down state power reduction
Lead-free
1
196-pin Ball Grid Array (BGA).
Devices that are lead-free are marked with a
circled “e1” and have the product code:
LUxxxxxx.
1
This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an
impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the
concentration of other Restriction on Hazardous Substances (RoHS)-banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks
In addition, this device has been tested and conforms to the same parametric specifications as previous
versions of the device.
For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales
representative.
317802-005
Revision 3.1
Revision History
Revision
Date
Jan 2002
Revision
1.0
•
•
•
Description
Added description for No Connect pins and corrected typographical errors.
Clarified EEPROM address map and word definitions for the 82551ER.
Added more detailed information for I
CC
in the DC specifications table.
Apr 2002
Mar 2003
Sep 2004
2.0
2.1
2.2
Changed document status to Intel Confidential.
•
•
•
•
•
•
•
•
Removed document status.
Removed references to MDI/MDI-X feature, not supported by the 82551ER.
Added references to the MDI/MDI-X feature.
Added lead-free information.
Removed EEPROM Map bit descriptions. These descriptions can now be found in the
82551QM/ER/IT EEPROM Map and Programming Information.
Added 82551ER Test Port Functionality (Chapter 10).
Added new values for RBIAS100 and RBIAS10. RBIAS100 = 649
and
RBIAS10 = 619
.
Removed all references to the 82551IT and 82551QM controllers. 82551IT and 82551QM
information can now be found in their respective datasheets.
Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to a 2-layer
0.32 mm wide-trace substrate. Refer to the section on Package and Pinout Information.
Updated the section describing “Multiple Priority Transmit Queues”.
Updated the section describing “VLAN Support”.
Added statement that no changes to existing soldering processes are needed for the 2-layer
0.32 mm wide-trace substrate change in the section describing “Package Information”.
Added a note for PHY signals RBIAS100 and RBIAS10 to Table 8.
Added Figure 28 “196 PBGA Package Pad Detail”. The figure shows solder resist opening and
metal diameter dimensions.
Added Section 13 “Reference Schematics”, updated Section 11.1 (changed Tcase to ambient)
and added ordering information to Section 1.4.
Updated Figures 31 and 32. Added Digital I/O and Crystal Input One (X1) Characteristics
(Tables 52 and 53). Updated Section 5.6.4.
Updated Figure 32: changed TEST pull down resistor value (62 K to 1 K).
Updated section 1.4 (changed A0 stepping to A1).
Updated Table 12 (changed words 30h:33h to reserved).
Updated Table 8 (X1 and X2 pin descriptions).
Updated Tables 52 and 53 (Digital I/O and crystal input one (X1) characteristics).
Nov 2004
Nov 2004
2.3
2.4
•
•
•
•
•
•
•
•
•
•
•
•
•
Jan 2005
Oct 2006
Sept 2007
Sept 2007
Mar 2008
Sept 2008
Nov 2008
2.5
2.6
2.7
2.8
2.9
3.0
3.1
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82551ER may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708-
296-9333
Intel
®
is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
Copyright © 2008, Intel Corporation.
* Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners’ benefit, without
intent to infringe.
ii
Datasheet
Networking Silicon — 82551ER
Contents
1.0
Introduction......................................................................................................................... 1
1.1
1.2
1.3
1.4
2.0
2.1
2.2
2.3
2.4
3.0
3.1
3.2
3.3
3.4
4.0
4.1
4.2
Overview ............................................................................................................... 1
Byte Ordering ........................................................................................................ 1
References ............................................................................................................ 1
Product Ordering Codes........................................................................................ 2
Parallel Subsystem Overview................................................................................ 3
FIFO Subsystem Overview ................................................................................... 3
10/100 Mbps Serial CSMA/CD Unit Overview ......................................................4
10/100 Mbps Physical Layer Unit.......................................................................... 4
Multiple Priority Transmit Queues ......................................................................... 5
Early Release ........................................................................................................ 5
Hardware Integrity Support ................................................................................... 6
Management Data Interface MDI/MDI-X Feature.................................................. 6
Signal Type Definitions ......................................................................................... 7
PCI Bus Interface Signals ..................................................................................... 8
4.2.1 Address and Data Signals ....................................................................... 8
4.2.2 Interface Control Signals ......................................................................... 8
4.2.3 System and Power Management Signals ............................................... 9
Local Memory Interface Signals .......................................................................... 10
Test Port Signals ................................................................................................ 11
PHY Signals ....................................................................................................... 12
Power and Ground Signals ................................................................................. 13
Device Initialization..............................................................................................15
5.1.1 Initialization Effects................................................................................. 15
PCI Interface ....................................................................................................... 16
5.2.1 Bus Operations....................................................................................... 16
5.2.2 Clock Run Signal.................................................................................... 24
5.2.3 Power Management Event ..................................................................... 25
PCI Power Management ..................................................................................... 25
5.3.1 Power States .......................................................................................... 25
5.3.2 Wake-up Events ..................................................................................... 29
Parallel Flash....................................................................................................... 30
Serial EEPROM Interface.................................................................................... 30
5.5.1 EEPROM Address Map.......................................................................... 32
10/100 Mbps CSMA/CD Unit............................................................................... 32
5.6.1 Full Duplex ............................................................................................. 33
5.6.2 Flow Control ........................................................................................... 33
5.6.3 Address Filtering Modifications .............................................................. 33
5.6.4 VLAN Support ........................................................................................ 33
Architectural Overview ....................................................................................................... 3
Performance Enhancements.............................................................................................. 5
Signal Descriptions.............................................................................................................7
4.3
4.4
4.5
4.6
5.0
5.1
5.2
Media Access Control Functional Description.................................................................. 15
5.3
5.4
5.5
5.6
Datasheet
iii
82551ER — Networking Silicon
5.7
6.0
6.1
Media Independent Interface (MII) Management Interface ................................. 34
100BASE-TX PHY Unit ....................................................................................... 35
6.1.1 100BASE-TX Transmit Clock Generation .............................................. 35
6.1.2 100BASE-TX Transmit Blocks ............................................................... 35
6.1.3 100BASE-TX Receive Blocks ................................................................ 35
6.1.4 100BASE-TX Link Integrity Auto-Negotiation......................................... 36
10BASE-T PHY Functions .................................................................................. 36
6.2.1 10BASE-T Transmit Clock Generation................................................... 36
6.2.2 10BASE-T Transmit Blocks.................................................................... 36
6.2.3 10BASE-T Receive Blocks..................................................................... 36
6.2.4 10BASE-T Link Integrity and Full Duplex ............................................... 37
Auto-Negotiation ................................................................................................. 37
6.3.1 Description ............................................................................................. 37
6.3.2 Parallel Detect and Auto-Negotiation ..................................................... 37
LED Description .................................................................................................. 38
Function 0: LAN (Ethernet) PCI Configuration Space ......................................... 41
7.1.1 PCI Vendor ID and Device ID Registers ................................................ 41
7.1.2 PCI Command Register ......................................................................... 42
7.1.3 PCI Status Register................................................................................ 43
7.1.4 PCI Revision ID Register........................................................................ 45
7.1.5 PCI Class Code Register ....................................................................... 45
7.1.6 PCI Cache Line Size Register................................................................ 45
7.1.7 PCI Latency Timer ................................................................................. 45
7.1.8 PCI Header Type ................................................................................... 45
7.1.9 PCI Base Address Registers.................................................................. 46
7.1.10 Base Address Registry Summary .......................................................... 47
7.1.11 PCI Subsystem Vendor ID and Subsystem ID Registers....................... 47
7.1.12 Capability Pointer ................................................................................... 48
7.1.13 Interrupt Line Register............................................................................ 48
7.1.14 Interrupt Pin Register ............................................................................. 48
7.1.15 Minimum Grant Register ........................................................................ 49
7.1.16 Maximum Latency Register.................................................................... 49
7.1.17 Capability ID Register ............................................................................ 49
7.1.18 Next Item Pointer ................................................................................... 49
7.1.19 Power Management Capabilities Register ............................................. 49
7.1.20 Power Management Control/Status Register (PMCSR)......................... 50
7.1.21 Data Register ......................................................................................... 51
LAN (Ethernet) Control/Status Registers ............................................................ 53
8.1.1 System Control Block Status Word ........................................................ 54
8.1.2 System Control Block Command Word.................................................. 55
8.1.3 System Control Block General Pointer................................................... 55
8.1.4 PORT ..................................................................................................... 55
8.1.5 Flash Control Register ........................................................................... 55
8.1.6 EEPROM Control Register..................................................................... 56
8.1.7 Management Data Interface Control Register........................................ 56
Physical Layer Functional Description ............................................................................. 35
6.2
6.3
6.4
7.0
7.1
Configuration Registers.................................................................................................... 41
8.0
Control/Status Registers .................................................................................................. 53
8.1
iv
Datasheet
Networking Silicon — 82551ER
8.2
9.0
9.1
8.1.8 Receive Direct Memory Access Byte Count........................................... 56
8.1.9 Flow Control Register............................................................................. 56
Statistical Counters ............................................................................................. 57
MDI Registers 0 - 7 ............................................................................................. 61
9.1.1 Register 0: Control Register .................................................................. 61
9.1.2 Register 1: Status Register ................................................................... 62
9.1.3 Register 2: PHY Identifier Register ....................................................... 63
9.1.4 Register 3: PHY Identifier Register ....................................................... 63
9.1.5 Register 4: Auto-Negotiation Advertisement Register ........................... 63
9.1.6 Register 5: Auto-Negotiation Link Partner Ability Register .................... 64
9.1.7 Register 6: Auto-Negotiation Expansion Register ................................. 64
MDI Registers 8:15..............................................................................................64
MDI Register 16:31 ............................................................................................. 65
9.3.1 Register 16: PHY Unit Status and Control Register .............................. 65
9.3.2 Register 17: PHY Unit Special Control Register ................................... 65
9.3.3 Register 18: PHY Address Register ....................................................... 66
9.3.4 Register 19: 100BASE-TX Receive False Carrier Counter ................... 66
9.3.5 Register 20: 100BASE-TX Receive Disconnect Counter ...................... 67
9.3.6 Register 21: 100BASE-TX Receive Error Frame Counter .................... 67
9.3.7 Register 22: Receive Symbol Error Counter ......................................... 67
9.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Coun-
ter 67
9.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter ............. 67
9.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter ..................... 68
9.3.11 Register 26: Equalizer Control and Status Register .............................. 68
9.3.12 Register 27: PHY Unit Special Control Register ................................... 68
9.3.13 Register 28: MDI/MDI-X Control Register .............................................. 69
9.3.14 Register 29: Hardware Integrity Control Register .................................. 69
Introduction.......................................................................................................... 71
Test Function Description.................................................................................... 71
10.2.1 Tristate ................................................................................................... 71
10.2.2 XOR Tree ............................................................................................... 72
Absolute Maximum Ratings................................................................................. 75
DC Specifications ............................................................................................... 76
AC Specifications ................................................................................................ 80
Timing Specifications .......................................................................................... 81
11.4.1 Clocks Specifications ............................................................................. 81
11.4.2 Timing Parameters ................................................................................. 82
Package Information ........................................................................................... 89
Pinout Information ............................................................................................... 91
12.2.1 Pin Assignments .................................................................................... 91
12.2.2 Ball Grid Array Diagram ......................................................................... 93
PHY Unit Registers ..........................................................................................................61
9.2
9.3
10.0
82551ER Test Port Functionality...................................................................................... 71
10.1
10.2
11.0
Electrical and Timing Specifications................................................................................. 75
11.1
11.2
11.3
11.4
12.0
Package and Pinout Information ...................................................................................... 89
12.1
12.2
Datasheet
v
