Dual Output RF Frequency Synthesizer
Data Sheet
844S42I
General Description
The 844S42I is a 3.3V compatible, PLL based clock synthesizer
targeted for clock generation in high-performance instrumentation,
networking and computing applications. Using either the serial (I
2
C)
or parallel programming interface, the 844S42I enables the
generation of clock frequencies in the range of 81MHz to 2592MHz.
The internal crystal oscillator uses the external quartz crystal as the
basis of its frequency reference. Alternatively, a LVCMOS compatible
clock signal can be used as PLL reference signal. The devices uses
an integer-N synthesizer architecture and is optimized for low-jitter
generation. The VCO within the PLL operates over a range of
1296MHz to 2592MHz. Its output is scaled by a divider that is
configured by either the I
2
C or parallel interfaces. The crystal
oscillator frequency f
XTAL
, the PLL pre-divider P, the feedback-divider
M and the PLL post-divider N determine the output frequency. The
feedback path of the PLL is internal.
The PLL post-dividers NA and NB are configured through either the
I
2
C or the parallel interfaces, each can provide one of seven division
ratios (1, 2, 3, 4, 6, 8, 16). This divider extends the performance of
the part while providing a typical 50% duty cycle. The high-frequency
outputs QA and QB are differential and are capable of driving a pair
of transmission lines. The positive supply voltage for the internal PLL
is separated from the power supply for the core logic and output
drivers to minimize noise induced jitter. The serial interface is I
2
C
compatible and provides read and write access to the internal PLL
configuration registers. The lock state of the PLL is indicated by the
LVCMOS-compatible LOCK_DT output. The 844S42I is packaged
in a 8mm x 8mm 56-lead VFQFN package.
Features
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Programmable frequency synthesis optimized for instrumentation,
networking and computing applications
81MHz to 2592MHz synthesized clock output signal
Two differential, universal LVDS or LVPECL compatible
high-frequency outputs
Output frequency programmable through 2-wire I
2
C bus or
parallel interface
On-chip crystal oscillator for reference frequency generation
Alternative LVCMOS/LVTTL compatible reference clock input
Clock stop and output enable functionality
PLL lock indicator output (LVCMOS/LVTTL)
LVCMOS/LVTTL compatible control inputs
Fully integrated PLL
SiGe Technology
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in a lead-free (RoHS 6) compliant package
Pin Assignment
ADR1
V
DDA
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
ADR0
nc
56 55 54 53 52 51 50 49 48 47 46 45 44 43
GND
nc
nBYPASS
nc
V
DD
REF_CLK
GND
REF_SEL
XTAL_IN
XTAL_OUT
nMR
LOCK_DT
LEV_SEL
V
DD
1
2
3
4
5
6
7
8
9
10
11
42
41
40
39
38
37
36
35
34
33
32
31
30
29
nc
V
DDOA
V
DDOA
QA
nQA
GND
GND
GND
GND
QB
nQB
V
DDOB
V
DDOB
nc
ICS844S42I
56-Lead VFQFN
8mm x 8mm x 0.925mm
package body
K Package
Top View
12
13
14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
GND
P
NA0
NA1
NA2
NB0
NB1
NB2
SDA
SCL
nPLOAD
GND
V
DD
V
DD
©2016 Integrated Device Technology, Inc
1
Revision A April 28, 2016
844S42I Data Sheet
Block Diagram
1
REF_CLK
XTAL_IN
OSC
f
QA
÷NA
f
VCO
0
1
f
REF
QA
f
QB
÷P
f
PD
PLL
0
QB
XTAL_OUT
REF_SEL
÷M
÷NB
SDA
SCL
ADR[1:0]
nPLOAD
M[9:0]
NA[2:0]
NB[2:0]
P
LEV_SEL
nBYPASS
nMR
PLL
Configuration
Registers
I
2
C Control
LOCK_DT
©2016 Integrated Device Technology, Inc
2
Revision A April 28, 2016
844S42I Data Sheet
Table 1. Pin Descriptions
Number
1, 7, 16, 27, 34,
35, 36, 37
2, 4, 29, 42, 43
3
5, 14, 15, 28
6
8
9,
10
11
12
13
17
18, 19, 20
21, 22, 23
24
25
26
30, 31
32, 33
38, 39
40, 41
44, 48, 49,
50, 53
45, 46, 47,
51, 52
54, 55
56
Name
GND
nc
nBYPASS
V
DD
REF_CLK
REF_SEL
XTAL_IN
XTAL_OUT
nMR
LOCK_DT
LEV_SEL
P
NA0, NA1, NA2
NB0, NB1, NB2
SDA
SCL
nPLOAD
V
DDOB
nQB, QB
nQA, QA
V
DDOA
M0, M4, M5,
M6, M9
M1, M2, M3,
M7, M8
ADR0, ADR1
V
DDA
Input
Output
Input
Input
Input
Input
I/O
I/O
Input
Power
Output
Output
Power
Input
Input
Input
Power
Pullup
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Pullup
Power
Unused
Input
Power
Input
Input
Pulldown
Pullup
Pulldown
Type
Description
Power supply ground.
Do not connect.
PLL bypass. LVCMOS/LVTTL interface levels.
Digital power supply pins.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Reference select pin. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Master reset. nMR resets the I
2
C, output dividers and the LOCK_DT.
LVCMOS/LVTTL interface levels.
Lock detect output. LVCMOS/LVTTL interface levels.
Output level select (LVDS and LVPECL).
LVCMOS/LVTTL interface levels.
Parallel configuration of PLL pre-divider. LVCMOS/LVTTL interface levels.
Parallel configuration of QA output dividers.
LVCMOS/LVTTL interface levels.
Parallel configuration of QB output dividers.
LVCMOS/LVTTL interface levels.
I
2
C data input/output pin.LVCMOS/LVTTL interface levels.
I
2
C clock.LVCMOS/LVTTL interface levels.
Selects the programming interface. LVCMOS/LVTTL interface levels.
Bank B output power supply pins.
QB differential clock output pair. LVPECL or LVDS interface levels.
QA differential clock output pair. LVPECL or LVDS interface levels.
Bank A output power supply pins.
Parallel configuration of PLL feedback dividers.
LVCMOS/LVTTL interface levels.
Bits 2 and 1 of the device I
2
C address. LVCMOS/LVTTL interface levels.
Internal PLL power supply pin.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
©2016 Integrated Device Technology, Inc
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Revision A April 28, 2016
844S42I Data Sheet
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
20
Maximum
Units
pF
k
k
R
PULLDOWN
Input Pulldown Resistor
R
OUT
Output Impedance
LOCK_DT
Functional Description
The 844S42I is a programmable high-frequency clock source (clock
synthesizer). The internal PLL generates a high frequency output
signal based on a low-frequency reference signal. The frequency of
the output signal is programmable and can be changed on the fly for
frequency margining purpose. The internal crystal oscillator uses the
parallel-resonance external quartz crystal as the basis of its
frequency reference. Alternatively, an LVCMOS compatible clock
signal can be used as a PLL reference signal. The frequency of the
internal crystal oscillator is divided by a selectable divider and then
multiplied by the PLL. The internal oscillator within the PLL operates
over a range of 1296 MHz to 2592 MHz. Its output is scaled by two
independent dividers that are configured by either the I2C or parallel
interfaces. The crystal oscillator frequency f
XTAL
, the PLL pre-divider
P, the feedback-divider M, and the PLL post-dividers NA, NB
determine the output frequency. The feedback path of the PLL is
internal.
The PLL post-dividers NA and NB are configured through either the
I
2
C or the parallel interfaces, and each can provide one of seven
division ratios (1, 2, 3, 4, 6, 8, 16) and can stop the output clock in a
logic low state. The divider extends the performance of the part while
providing a typical 50% duty cycle. The high-frequency outputs, QA
and QB, are differential and are capable of driving a pair of
transmission lines. The differential outputs are configured as LVDS
or LVPECL by the control input LEV_SEL. The positive supply
voltage for the internal PLL is separated from the power supply for
the core logic and output drivers to minimize noise induced jitter.
The configuration logic has two sections: I
2
C and parallel. The
parallel interface uses the values at the M[9:0], NA[2:0], NB[2:0] and
P parallel inputs to configure the internal PLL dividers. The parallel
programming interface has priority over the serial I
2
C interface. The
serial interface is I
2
C compatible and provides read and write access
to the internal PLL configuration registers.The lock state of the PLL
is indicated by the LVCMOS-compatible LOCK_DT output.
©2016 Integrated Device Technology, Inc
4
Revision A April 28, 2016
844S42I Data Sheet
Device Configuration
The ICS844S42I supports an output frequency range of 81MHz to
2592MHz. The output frequency f
OUT
is a function of the reference
frequency f
REF
and the three internal PLL dividers P, M, and N. f
OUT
can be represented by this formula:
f
OUT
= (f
REF
÷ P) · M ÷ (NA, NB)
The M, N and P dividers require a configuration by the user to
achieve the desired output frequency. The output dividers NA, NB
determine the achievable output frequency range (see Table 3A).
The PLL feedback-divider M is the frequency multiplication factor
and the main variable for frequency synthesis. For a given reference
frequency f
REF
, the PLL feedback-divider M must be configured to
match the specified VCO frequency range in order to achieve a valid
PLL configuration:
f
VCO
= (f
REF
÷ P) · M and 1296MHz
f
VCO
2592MHz
The output frequency may be changed at any time by changing the
value of the PLL feedback divider M. The smallest possible output
frequency change is the synthesizer granularity G (difference in f
OUT
when incrementing or decrementing M). At a given reference
frequency, G is a function of the PLL pre-divider P and post-divider
N:
G = f
REF
÷ (P · NA, NB)
The purpose of the PLL pre-divider P is to situate the PLL into the
specified VCO frequency range f
VCO
(in combination with M). For a
given output frequency, P = ÷4 results in a smaller output frequency
granularity G, P = ÷2 results a larger output frequency granularity G
and also decreases the PLL bandwidth compared to the P = ÷4
setting. The following example illustrates the output frequency range
of the 844S42I using a 16MHz reference frequency.
Table 3A. Device Configuration Table for f
REF
= 16MHz)
Output Frequency (MHz)
1296 – 2592
NA, NB
1
162 – 324
324 – 648
648 – 1296
2
162 – 324
324 – 648
432 – 864
3
162 – 324
324 – 648
324 – 648
4
162 – 324
324 – 648
216 – 432
6
162 – 324
324 – 648
162 – 324
8
162 – 324
324 – 648
81 – 162
16
162 – 324
2
0.5
2
4
1
0.25
2
4
1.33
0.5
2
4
2
0.66
2
4
2.66
1
2
4
4
1.33
2
4
8
2
M
324 – 648
P
4
G (MHz)
4
©2016 Integrated Device Technology, Inc
5
Revision A April 28, 2016
