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首页 > 器件类别 > 无线/射频/通信 > 无线收发芯片

A71X25AQFI/Q

器件类别：无线/射频/通信    无线收发芯片   

厂商名称：笙科

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A7125
2.4GHz FSK Transceiver
Document Title
A7125 Data Sheet, 2.4GHz FSK Transceiver with 2M / 1Mbps data rate
Revision History
Rev. No.
0.0
0.1
0.2
History
Initial issue.
Logo change.
Modify PIN Configuration and Description, Block Diagram,
Electrical Specifications, Diagram of State Machine. Add
Control Register and Function Description.
Add Power Saving FIFO Mode.
Rename GPIO1 and GPIO2 into GIO1 and GIO2.
Modify register recommended value IGFI [2:0] = [000]
Modify register recommended value IGFQ [2:0] = [000]
Delete TWWS function
Issue Date
Aug. 31, 2007
Oct. 18, 2007
July 31, 2008
Remark
0.4
EN
October 06, 2008
June 11, 2009
Feb., 2010
Nov., 2010
Nov. 30, 2010
Jul. 2011
0.3
August 31, 2008
1.1
1.2
1.3
Add Note 8 (regulator settling time) in chapter 8.
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0.5
Modify register recommended value
Delay Register I (17h): PDL= [000]
Delay Register II (18h): WSEL= [011]
Battery Detect Register (2Ch): QDS = [1]
Crystal Test Register (32h): XCP= [00]
IFAT Register (36h): IGFI [2:0] = [111], IGFQ [2:0] = [111]
Modify PLL to WPLL settling time when PDL=[000]
If LO is changed, from 20 us to 30 us
If LO is fixed, from 20 us to 10 us
Delete Ext Voltage Measurement function
Add EOPD output to GIO2
Add PASW output to GIO2
Add EOPDS Register
Add section 16.5
Modify register recommended value
ADC Control (1Fh): CDM= [0]
Modify recommended timing of PASW
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Modify the tape reel information and the add Shenzhen
office address.
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Important Notice:
AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service
without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for
use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such
applications is understood to be fully at the risk of the customer.
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Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Full
Production
Full
Production
Full
Production
Full
Production
A7125
2.4GHz FSK Transceiver
Table of Contents
1. Typical Application ..................................................................................................................................................... 5
2. General Description ................................................................................................................................................... 5
3. Feature ..................................................................................................................................................................... 5
4. PIN Configuration ...................................................................................................................................................... 6
5. PIN Description (I: Input, O: Output, I/O: Input or Output, G: Ground, D: Digital)........................................................... 7
6. Block Diagram ........................................................................................................................................................... 8
7. Absolution Maximum Rating ....................................................................................................................................... 9
8. Electrical Specifications............................................................................................................................................ 10
General ................................................................................................................................................................ 10
Phase Locked Loop .............................................................................................................................................. 10
Transmitter ........................................................................................................................................................... 10
Receiver............................................................................................................................................................... 10
Regulator ............................................................................................................................................................. 10
Digital IO DC characteristics...................................................................................................................................11
9. Control Register....................................................................................................................................................... 12
9.1 Control Register Table..................................................................................................................................... 12
9.2 Control Register Description............................................................................................................................ 15
9.2.1 Mode Register (Address: 00h) ............................................................................................................... 15
9.2.2 Mode Control Register (Address: 01h) ................................................................................................... 15
9.2.3 Calibration Control Register (Address: 02h)............................................................................................ 16
9.2.4 FIFO Register I (Address: 03h) .............................................................................................................. 16
9.2.5 FIFO Register II (Address: 04h) ............................................................................................................. 16
9.2.6 FIFO DATA Register (Address: 05h)....................................................................................................... 16
9.2.7 ID DATA Register (Address: 06h) ........................................................................................................... 16
9.2.8 RC OSC Register I (Address: 07h)......................................................................................................... 17
9.2.9 RC OSC Register II (Address: 08h)........................................................................................................ 17
9.2.10 RC OSC Register III (Address: 09h)..................................................................................................... 17
9.2.11 CKO Pin Control Register (Address: 0Ah)............................................................................................. 17
9.2.12 GIO1 Pin Control Register (Address: 0Bh)............................................................................................ 17
9.2.13 GIO2 Pin Control Register (Address: 0Ch) ........................................................................................... 18
9.2.14 Data Rate Clock Register (Address: 0Dh)............................................................................................. 19
9.2.15 PLL Register I (Address: 0Eh).............................................................................................................. 21
9.2.16 PLL Register II (Address: 0Fh)............................................................................................................. 21
9.2.17 PLL Register III (Address: 10h) ............................................................................................................ 21
9.2.18 PLL Register IV (Address: 11h) ............................................................................................................ 21
9.2.19 PLL Register V (Address: 12h)............................................................................................................. 21
9.2.20 Channel Group Register I (Address: 13h) ............................................................................................. 21
9.2.21 Channel Group Register II (Address: 14h) ............................................................................................ 22
9.2.22 TX Register I (Address: 15h)................................................................................................................ 22
9.2.23 TX Register II (Address: 16h)............................................................................................................... 22
9.2.24 Delay Register I (Address: 17h) ........................................................................................................... 23
9.2.25 Delay Register II (Address: 18h) .......................................................................................................... 23
9.2.26 RX Register (Address: 19h) ................................................................................................................. 24
9.2.27 RX Gain Register I (Address: 1Ah)....................................................................................................... 24
9.2.28 RX Gain Register II (Address: 1Bh)...................................................................................................... 24
9.2.29 RX Gain Register III (Address: 1Ch)..................................................................................................... 25
9.2.30 RX Gain Register IV (Address: 1Dh) .................................................................................................... 25
9.2.31 RSSI Threshold Register (Address: 1Eh).............................................................................................. 25
9.2.32 ADC Control Register (Address: 1Fh)................................................................................................... 25
9.2.33 Code Register I (Address: 20h) ............................................................................................................ 26
9.2.34 Code Register II (Address: 21h)........................................................................................................... 26
9.2.35 Code Register III (Address: 22h) .......................................................................................................... 26
9.2.36 IF Calibration Register I (Address: 23h)................................................................................................ 26
9.2.37 IF Calibration Register II (Address: 24h)............................................................................................... 27
9.2.38 VCO Current Calibration Register (Address: 25h) ................................................................................. 27
9.2.39 VCO Bank Calibration Register I (Address: 26h)................................................................................... 27
9.2.40 VCO Bank Calibration Register II (Address: 27h).................................................................................. 28
9.2.41 VCO Deviation Calibration Register I (Address: 28h) ............................................................................ 28
9.2.42 VCO Deviation Calibration Register II (Address: 29h) ........................................................................... 28
9.2.43 VCO Deviation Calibration Register III (Address: 2Ah) .......................................................................... 28
9.2.44 VCO Modulation Delay Register (Address: 2Bh)................................................................................... 29
9.2.45 Battery Detect Register (Address: 2Ch)................................................................................................ 29
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9.2.46 TX test Register (Address: 2Dh)........................................................................................................... 29
9.2.47 RX DEM test Register I (Address: 2Eh)................................................................................................ 29
9.2.48 RX DEM test Register II (Address: 2Fh) ............................................................................................... 30
9.2.49 Charge Pump Current Register I (Address: 30h)................................................................................... 30
9.2.50 Charge Pump Current Register II (Address: 31h).................................................................................. 30
9.2.51 Crystal test Register (Address: 32h) ..................................................................................................... 30
9.2.52 PLL test Register (Address: 33h).......................................................................................................... 30
9.2.53 VCO test Register (Address: 34h) ........................................................................................................ 31
9.2.54 RF Analog test Register (Address: 35h)................................................................................................ 31
9.2.55 IFAT Register (Address: 36h) ............................................................................................................... 31
9.2.56 Channel Select Register (Address: 37h)............................................................................................... 32
9.2.57 VRB Register (Address: 38h) ............................................................................................................... 32
10. SPI........................................................................................................................................................................ 33
10.1 SPI Format ................................................................................................................................................... 34
10.2 SPI Timing Characteristic .............................................................................................................................. 34
10.3 SPI Timing Chart........................................................................................................................................... 34
10.3.1 Timing Chart of 3-wire SPI ................................................................................................................... 34
10.3.2 Timing Chart of 4-wire SPI ................................................................................................................... 35
10.4 Strobe Commands ........................................................................................................................................ 35
10.4.1 Strobe Command - Sleep Mode ........................................................................................................... 36
10.4.2 Strobe Command - ldle Mode............................................................................................................... 36
10.4.3 Strobe Command - Standby Mode........................................................................................................ 37
10.4.4 Strobe Command - PLL Mode.............................................................................................................. 37
10.4.5 Strobe Command - RX Mode ............................................................................................................... 38
10.4.6 Strobe Command - TX Mode................................................................................................................ 38
10.4.7 Strobe Command – FIFO Write Pointer Reset ...................................................................................... 38
10.4.8 Strobe Command – FIFO Read Pointer Reset ...................................................................................... 39
10.5 Reset Command........................................................................................................................................... 39
10.6 ID Accessing Command ................................................................................................................................ 39
10.6.1 ID Write Command.............................................................................................................................. 40
10.6.2 ID Read Command.............................................................................................................................. 40
10.7 FIFO Accessing Command............................................................................................................................ 40
10.7.1 TX FIFO Write Command .................................................................................................................... 40
10.7.2 Rx FIFO Read Command .................................................................................................................... 41
11. State machine........................................................................................................................................................ 42
11.1 Key states ..................................................................................................................................................... 42
11.1.1 Standby mode ..................................................................................................................................... 42
11.1.2 Sleep mode ......................................................................................................................................... 43
11.1.3 ldle mode ............................................................................................................................................ 43
11.1.4 PLL mode............................................................................................................................................ 43
11.1.5 TX mode ............................................................................................................................................. 43
11.1.6 RX mode............................................................................................................................................. 43
11.1.7 CAL mode ........................................................................................................................................... 44
11.2 Normal FIFO Mode........................................................................................................................................ 45
11.3 Quick FIFO Mode.......................................................................................................................................... 47
11.4 Power Saving FIFO Mode.............................................................................................................................. 48
11.5 Quick Direct Mode......................................................................................................................................... 51
12 Crystal Oscillator Circuit.......................................................................................................................................... 54
12.1 Use External Crystal...................................................................................................................................... 54
12.2 Use External Clock........................................................................................................................................ 54
13. System Clock ........................................................................................................................................................ 55
13.1 Derive System Clock ..................................................................................................................................... 55
13.2 Data Rate ..................................................................................................................................................... 56
14. Transceiver Frequency........................................................................................................................................... 57
14.1 LO Frequency Setting ................................................................................................................................... 58
14.2 IF Side Band Select ...................................................................................................................................... 61
14.2.1 Auto IF Exchange................................................................................................................................ 62
14.2.2 Fast Exchange .................................................................................................................................... 62
14.3 Band Edge Frequency Setting ....................................................................................................................... 63
14.4 Frequency Compensation.............................................................................................................................. 65
15. Calibration............................................................................................................................................................. 67
15.1 Calibration Procedure.................................................................................................................................... 67
15.2 IF Filter Bank Calibration ............................................................................................................................... 67
15.3 RSSI Calibration ........................................................................................................................................... 67
15.4 VCO Current Calibration................................................................................................................................ 68
15.5 VCO Bank Calibration ................................................................................................................................... 68
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15.6 VCO Deviation Calibration............................................................................................................................. 68
15.7 Channel Group Function ............................................................................................................................... 68
16. FIFO (First In First Out).......................................................................................................................................... 70
16.1 Packet Format of FIFO mode ........................................................................................................................ 70
16.2 Bit Stream Process........................................................................................................................................ 71
16.3 Transmission Time ........................................................................................................................................ 71
16.4 Usage of TX and RX FIFO............................................................................................................................. 72
16.4.1 Easy FIFO........................................................................................................................................... 72
16.4.2 Segment FIFO..................................................................................................................................... 73
16.4.3 FIFO Extension ................................................................................................................................... 76
16.5 Optimize Throughput..................................................................................................................................... 80
17. ADC (Analog to Digital Converter) .......................................................................................................................... 82
17.1 Temperature Measurement............................................................................................................................ 82
17.2 RSSI Measurement....................................................................................................................................... 82
17.3 Carrier Detect ............................................................................................................................................... 84
18. Battery Detect........................................................................................................................................................ 85
19. Application Circuit Example .................................................................................................................................... 86
20. Abbreviations......................................................................................................................................................... 87
20. Abbreviations......................................................................................................................................................... 88
21. Ordering Information .............................................................................................................................................. 88
22. Package Information .............................................................................................................................................. 89
23. Top Marking Information......................................................................................................................................... 90
24. Reflow Profile ........................................................................................................................................................ 91
25. Tape Reel Information............................................................................................................................................ 92
26. Product Status ....................................................................................................................................................... 93
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A7125
2.4GHz FSK Transceiver
1. Typical Application
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2.4GHz ISM band Communication System
2.4GHz Remote Control
Wireless Keyboard and Mouse
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Wireless Intelligent sports
Wireless Toy and Gaming
Wireless Audio/Video Streaming
2. General Description
A7125 is a high performance and low cost 2.4GHz ISM band wireless transceiver. It integrates high sensitivity receiver
(-90dBm @2Mbps), high efficiency power amplifier (up to 3dBm), frequency synthesizer and base-band modem. In typical
system, A7125 is used together with MCU (microcontroller) with very few external passive components. A7125 supports
both FIFO mode and direct mode that contains clock recovery circuit CKO pin to MCU.
A7125 supports very fast settling time (90 us) for frequency hopping system. For packet handling, A7125 has built-in
separated 64-bytes TX/RX FIFO (could be extended to 256 bytes) for data buffering and burst transmission, CRC for error
detection, FEC for 1-bit data correction per code word, RSSI for clear channel assessment, data whitening for data
encryption/decryption, thermal sensor for monitoring relative temperature. Those functions are very easy to use while
developing a wireless system. All features are integrated in a small QFN 4X4 20 pins package.
A7125’s data rate is up to 2Mbps and can be easily programmed to 1Mbps or 2 Mbps via 3-wire or 4-wire SPI bus. For
power saving, A7125 supports sleep mode, idle mode, standby mode. For easy-to-use, A7125 has an unique SPI
command set called
Strobe command
that are used to control A7125’s state machine. Based on Strobe commands, from
power saving, TX delivery, RX receiving, channel monitoring, frequency hopping to auto calibrations, MCU only needs to
define A7125’s control registers and send Strobe commands via SPI bus. In addition, A7125 supports two general purpose
I/O pins, GIO1 and GIO2, to inform MCU its status so that MCU could use either polling or interrupt scheme to do radio
control. Therefore, it is very easy to monitor transmission between MCU and A7125 because of its digital interface.
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Small size (QFN 4X4, 20 pins).
Support 2400 ~ 2483.5 MHz ISM band.
FSK modulation.
Programmable data rate to 1Mbps or 2Mbps.
Low current consumption: RX 17mA, TX 15.7mA (at 0dBm output power).
Low sleep current (1.5uA).
Programmable RF output power
-20dBm
~ 3dBm.
Very High sensitivity
(-90dBm@2Mbps,
-92dBm@1Mbps).
On chip regulator, supports input voltage 2.0 ~ 3.6V.
Easy to use
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Support 3-wire or 4-wire SPI.
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Unique Strobe command via SPI.
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Change frequency channel by ONE register setting.
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8-bits Digital RSSI for clear channel indication.
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Fast exchange mode during TRX role switching.
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Auto RSSI measurement.
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Auto Calibrations.
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Auto IF function.
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Auto CRC Check.
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Auto FEC by (7, 4) Hamming code (1 bit error correction / code word).
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Data Whitening for encryption and decryption.
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Separated 64 bytes RX and TX FIFO.
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Easy FIFO / Segment FIFO / FIFO Extension (up to 256 bytes).
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Support direct mode with recovery clock output to MCU.
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Support direct mode with frame sync signal to MCU.
Support low cost crystal (6 / 8 /12 / 16MHz).
Support low accuracy crystal within ± 50ppm.
Support Auto Frequency Compensation.
Support crystal sharing, (1 / 2 / 4 / 8MHz) to MCU.
Fast settling time synthesizer for frequency hopping system.
Built-in thermal sensor for monitoring relative temperature.
Built-in Battery Detector.
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3. Feature
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