A7129
FSK/GFSK Sub 1GHz Transceiver
Document Title
315/433/480/510/868/915MHz FSK/GFSK Transceiver with 2K ~ 250Kbps
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
History
Initial issue
Modify description of Ch 12 and Ch 13
Update specification and A50 application circuit
Update Figure 13.1, PLLII (02h) and Fdev (06h, page0)
formula
Update register setting recommendation. Add Ch 20. Modify
VCOP and VCON position and ESD descriptions
Issue Date
Sep., 2011
Feb., 2012
April, 2012
June, 2012
Oct., 2012
Remark
Objective
Preliminary
Preliminary
Preliminary
Preliminary
Important Notice:
AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service
without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable
for use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such
applications is understood to be fully at the risk of the customer.
Oct., 2012, Version 0.4
(PRELIMINARY)
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
Table of contents
1. Typical Applications................................................................................................................................................. 4
2. General Description................................................................................................................................................. 4
3. Features ................................................................................................................................................................. 4
4. Pin Configurations ................................................................................................................................................... 5
5. RF Chip Block Diagram ........................................................................................................................................... 6
6. Pin Descriptions ...................................................................................................................................................... 6
7. Absolute Maximum Ratings ..................................................................................................................................... 7
8. Specification............................................................................................................................................................ 8
9. Control Register .................................................................................................................................................... 12
9.1 Control Register Table................................................................................................................................... 12
9.2 Control Register Description.......................................................................................................................... 13
9.2.1 System clock (Address: 00h) ............................................................................................................... 13
9.2.2 PLL I (Address: 01h) ........................................................................................................................... 13
9.2.3 PLL II (Address: 02h) .......................................................................................................................... 14
9.2.4 PLL III (Address: 03h) ......................................................................................................................... 14
9.2.5 PLL IV (Address: 04h) ......................................................................................................................... 14
9.2.6 PLL V (Address: 05h) .......................................................................................................................... 15
9.2.7 PLL VI (Address: 06h) ......................................................................................................................... 15
9.2.8 Crystal (Address: 07h)......................................................................................................................... 15
9.2.9 TX I (Address: 08h) Page 0 ................................................................................................................. 16
9.2.9.1 WOR I (Address: 08h) Page1 ........................................................................................................... 16
9.2.9.2 WOR II (Address: 08h) Page 2 ......................................................................................................... 17
9.2.9.3 RF Current (Address: 08h) Page 3.................................................................................................... 17
9.2.9.4 Power Manage (Address: 08h) Page 4.............................................................................................. 18
9.2.9.5 AGC RSSI Threshold (Address: 08h) Page 5 .................................................................................... 18
9.2.9.6 AGC Control(Address: 08h) Page 6 .................................................................................................. 19
9.2.9.7 AGC Control II(Address: 08h) Page 7 ............................................................................................... 19
9.2.9.8 GPIO (Address: 08h) Page 8 ........................................................................................................... 20
9.2.9.9 CKO (Address: 08h) Page 9 ............................................................................................................. 21
9.2.9.10 VCO current (Address: 08h) Page 10.............................................................................................. 22
9.2.9.11 Channel Group (I) (Address: 08h) Page 11...................................................................................... 23
9.2.9.12 Channel Group (II) (Address: 08h) Page 12..................................................................................... 23
9.2.9.13 FIFO (Address: 08h) Page 13 ......................................................................................................... 23
9.2.9.14 Code (Address: 08h) Page 14......................................................................................................... 23
9.2.9.15 WCAL (Address: 08h) Page 15....................................................................................................... 24
9.2.10.0 TX II (Address: 09h) Page 0............................................................................................................ 24
9.2.10.1 IFI (Address: 09h) Page1................................................................................................................ 25
9.2.10.2 IFII (Address: 09h) Page2............................................................................................................... 25
9.2.10.3 ACK (Address: 09h) Page3............................................................................................................. 25
9.2.10.4 ART (Address: 09h) Page4 ............................................................................................................. 27
9.2.11 RX I (Address: 0Ah) .......................................................................................................................... 27
9.2.12 RX II (Address: 0Bh) ......................................................................................................................... 28
9.2.13 ADC (Address: 0Ch).......................................................................................................................... 28
9.2.14 Pin Control (Address: 0Dh)................................................................................................................ 29
9.2.15 Calibration (Address: 0Eh)................................................................................................................. 30
9.2.16 Mode control (Address: 0Fh) ............................................................................................................. 31
10. SPI (3-wire) ......................................................................................................................................................... 32
10.1 SPI Format ................................................................................................................................................. 32
10.2 SPI Timing Chart ........................................................................................................................................ 33
10.3 Control register access ............................................................................................................................... 33
10.4 SPI Timing Specification ............................................................................................................................. 33
10.5 Reset Command......................................................................................................................................... 34
10.6 Reset TX FIFO Pointer................................................................................................................................ 34
10.7 Reset Rx FIFO Pointer................................................................................................................................ 34
10.8 ID Read/Write Command ............................................................................................................................ 34
10.9 FIFO R/W Command .................................................................................................................................. 35
11. Crystal Oscillator ................................................................................................................................................. 36
11.1 Use External Crystal ................................................................................................................................... 36
11.2 Use External Clock ..................................................................................................................................... 36
12. System Clock ...................................................................................................................................................... 37
12.1 Clock Domain ............................................................................................................................................. 37
12.2 System Clock and IF Filter .......................................................................................................................... 38
12.3 Example of 10Kbps data rate by 12.8MHz Xtal ............................................................................................ 38
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
12.4 Example of special data rate by 19.6608MHz Xtal........................................................................................ 39
13. Tranceiver Frequency .......................................................................................................................................... 41
14. State machine ..................................................................................................................................................... 42
14.1 Key Strobe Commands ............................................................................................................................... 42
14.2 FIFO mode ................................................................................................................................................. 42
14.3 Direct mode................................................................................................................................................ 44
15. Calibration........................................................................................................................................................... 46
15.1 IF Calibration Process................................................................................................................................. 46
15.2. VCO band Calibration Process................................................................................................................... 46
16. FIFO (First In First Out)........................................................................................................................................ 47
16.1 Packet Format ............................................................................................................................................ 47
16.2 Bit Stream Process ..................................................................................................................................... 47
16.3 Transmission Time...................................................................................................................................... 48
16.4 Usage of TX and RX FIFO .......................................................................................................................... 48
16.4.1 Easy FIFO Mode............................................................................................................................... 49
16.4.2 Segment FIFO .................................................................................................................................. 49
16.4.3 FIFO Extension................................................................................................................................. 51
17. Analog Digital Converter ...................................................................................................................................... 55
17.1 Temperature Measurement ......................................................................................................................... 55
17.2 RSSI Measurement..................................................................................................................................... 55
17.3 Carrier detect.............................................................................................................................................. 55
18. Battery Detect ..................................................................................................................................................... 55
19. TX power setting ................................................................................................................................................. 56
20. Low Current RX mode setting .............................................................................................................................. 56
21. Application Circuit................................................................................................................................................ 57
21.1 MD7129-A40 (434MHz Band) ..................................................................................................................... 57
21.2 MD7129-A50 (470MHz~510MHz Band)....................................................................................................... 58
21.3 MD7129-A80 (868MHz Band) ..................................................................................................................... 59
22. Abbreviations ...................................................................................................................................................... 60
23. Ordering Information............................................................................................................................................ 60
24. Package Information............................................................................................................................................ 61
25. Top Marking Information....................................................................................................................................... 62
26. Reflow Profile ...................................................................................................................................................... 63
27. Tape Reel Information ......................................................................................................................................... 64
28. Product Status..................................................................................................................................................... 66
Oct., 2012, Version 0.4
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
1. Typical Applications
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ISM Band Data Communication
Wireless Remote Controller
RKE (Remote Keyless Entry)
Building Automation
Home Security
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Wireless Sensor Networking
Energy Control and Management
RKE (Remote Keyless Entry)
AMR (Auto Metering Reading)
2. General Description
A7129 is a monolithic low-IF architecture CMOS FSK/GFSK TRX for wireless applications in the 315/433/470/510/868/
915MHz ISM bands. This device is especially suitable for battery-powered application and the 470MHz ~ 510MHz
wireless AMR (Auto Meter Reading) in China and 868.3MHz wireless M-bus in Europe.
A7129 is one of AMICCOM’s
Mini Power Consumption Family
in sub 1GHz ISM band product line. A7129 is optimized
for very low power consumption (i.e. 434MHz band, 3.8mA @ RX mode and 24 mA @ TX mode,10.5dBm). In addition,
A7129 can offer a very good link budget with a high efficient class-E power amplifier up to 12 dBm and a low phase
noise receiver (- 110 dBm RX sensitivity @ 100Kbps / FSK / 433.92MHz). Therefore, A7129 is very suitable for battery
powered application with a nice LOS (line-of-sight) wireless range.
A7129 incorporates a baseband modem with the programmable data rate divider from 2K to 250Kbps. For a battery
powered system, A7129 supports fast PLL settling time (120 us), Xtal settling time (1100 us) and on-chip Regulator
settling time (850 us) to reduce average power consumption. The RF synthesizer contains a VCO and a low noise
fractional-N PLL with an output channel frequency resolution of 366 Hz. The VCO frequency operates at to the wanted
radio frequency to cover all RF band. Since A7129 is a low-IF architecture TRX with programmable IFBW (IF Filter
Bandwidth, 50KHz/100KHz/150KHz/250KHz), the RXLO shall be configured to offset an intermediate frequency (IF) to
TXRF regarding to the IFBW setting.
A7129’s
control registers
are accessed via 3-wire or 4-wire SPI interface including TX/RF FIFO, VCO frequency, to
chip calibration procedures. Another one, via SPI as well, is the unique
Strobe command,
A7129 can be controlled from
power saving mode (deep sleep, sleep, idle, standby), PLL mode, TX mode and RX mode. In addition to SPI, the digital
connections between A7129 and MCU are GIO1 and GIO2 (multi-function GPIO) to indicate A7129’s status so that MCU
could use either polling or interrupt for radio control.
For packet handling, A7129 supports direct mode and FIFO mode. In direct mode, MCU or Encoder shall deliver the
defined packet (preamble + sync word + payload) to GIO1 or GIO2/TXD pin. Then, in RX mode, MCU or Decoder can
receive the coming packet (preamble + sync word + payload) in bit sequence from GIO1 or GIO2/RXD pin.
In FIFO mode, preamble is self-generated by A7129. User just needs to assign the sync word to this device by ID R/W
command via SPI. For payload, the built-in separated 64-bytes TX/RX FIFO are used to be this purpose to let user R/W
the wanted payload. User can also enable additional packet features like CRC for error detection, FEC (hamming 7 by 4)
for 1-bit data correction per code word, Manchester coding, as well as data whitening for data encryption / decryption.
Additional device features such as on-chip regulator, RSSI for clear channel assessment, a thermal sensor, low battery
detector, carrier detect, preamble detect, frame sync in FIFO mode, auto-ack and auto-resend, AIF (Auto IF function),
AFC (Auto Frequency compensation), Auto calibration (VCO, IF Filter), PLL/CLK Generator, on-chip compensated
capacitors of Xtal loading, and WOR (Wake on RX) to support the ability to periodically wake up from sleep mode to RX
mode and listen for incoming packets without MCU interaction, can be used to simplify system development and cost.
Overall, A7129’s highly integrated features and low current consumption offer a reduced BOM cost for a high
performance ISM bands product. All features are integrated in a small QFN 4X4 24 pins package.
3. Features
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Small size (QFN 4X4, 24 pins).
Frequency band: 315/433/470/510/868/915 MHz.
FSK and GFSK modulation.
Programmable data rate from 2Kbps to 250Kbps.
Programmable TX power level from – 40 dBm to 12 dBm.
On chip regulator, supports input voltage 2.2 ~ 3.6 V.
Deep sleep current (0.5uA).
Sleep current (1.5 uA).
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AMICCOM Electronics Corporation
A7129
FSK/GFSK Sub 1GHz Transceiver
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Ultra Low Current Consumption
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RX Current consumption (AGC Off) 434MHz: 3.8mA.
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RX Current consumption (AGC Off) 868MHz: 4.4mA.
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TX Current consumption 433MHz: 24mA @ 10.5dBm.
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TX Current consumption 868MHz: 24mA @ 10dBm.
Fast PLL settling time (120 us).
Supports low cost crystal (12.8 / 16 / 19.2 MHz).
AGC (Auto Gain Control) for the wide RSSI dynamic range.
Programmable IF filter bandwidth (50KHz / 100KHz / 150KHz / 250KHz).
High RX sensitivity, i.e. 490MHz.
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-118dBm at 2Kbps on-air data rate.
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-115dBm at 50Kbps on-air data rate.
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-109dBm at 100Kbps on-air data rate.
Easy to use
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Support 3-wire or 4-wire SPI.
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Unique Strobe command via SPI.
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AGC ON with 9-bits RSSI.
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AGC OFF with 8-bits RSSI.
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Auto Calibrations (VCO, IF Filter, RSSI).
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Auto IF function.
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Auto Frequency Compensation.
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Auto CRC Filtering.
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Auto FEC by (7, 4) Hamming code (1 bit error correction / code word).
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Auto-resend (max 15 cycles).
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Auto-acknowledgement.
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Manchester encoding.
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Programmable carrier sense indicator.
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Data Whitening for payload encryption and decryption.
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Separated 64 bytes RX and TX FIFO.
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Easy FIFO / Segment FIFO / FIFO Extension (16K bytes to infinite).
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Support FIFO mode with frame sync to MCU.
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Support direct mode with recovery clock output to MCU.
On chip 8-bits ADC.
Low Battery indication.
On-chip low power RC oscillator for WOT and WOR (Wake on TX/RX) function.
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4. Pin Configurations
BP_BG
VDD_A
REGI
22
24
23
21
CKO
20
RSSI
GND
RFI
RFO
VDD_TX
VDD_VCO
19
GIO2
GIO1
1
2
18
VDD_D
VDD_D
SDIO
SCK
SCS
GND
17
3
16
4
5
15
14
6
13
10
11
VDD_PLL
VCON
VCOP
Figure 4.1 QFN4x4 Package Top View
Oct., 2012, Version 0.4
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AMICCOM Electronics Corporation
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