Dual-Channel, 12-Bit, 80 MSPS ADC
with Analog Input Signal Conditioning
AD13280
FEATURES
Dual 80 MSPS, minimum sample rate
Channel-to-channel matching, ±1% gain error
90 dB channel-to-channel isolation
DC-coupled signal conditioning
80 dB spurious-free dynamic range
Selectable bipolar inputs (±1 V and ±0.5 V ranges)
Integral single-pole, low-pass Nyquist filter
Twos complement output format
3.3 V compatible outputs
1.85 W per channel
APPLICATIONS
Radar processing (optimized for I/Q baseband operation)
Phased array receivers
Multichannel, multimode receivers
GPS antijamming receivers
Communications receivers
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
Guaranteed sample rate of 80 MSPS.
Input signal conditioning; gain and impedance match.
Single-ended, differential, or off-module filter option.
Fully tested/characterized full channel performance.
FUNCTIONAL BLOCK DIAGRAM
AMP-IN-A-2
AMP-IN-A-1
AMP-IN-B-2
AMP-IN-B-1
AMP-OUT-A
A–IN
A+IN
AMP-OUT-B
B+IN
AD13280
DROUTA
D0A (LSB)
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
9
VREF
DROUT
12
100Ω OUTPUT TERMINATORS
TIMING
3
VREF
DROUT
12
100Ω OUTPUT TERMINATORS
7
5
TIMING
B–IN
DROUTB
ENCODEB
ENCODEB
D11B (MSB)
D10B
D9B
D8B
02386-001
D7B
D11A
(MSB)
D0B D1B D2B
(LSB)
D3B D4B
D5B
D6B
ENCODEA ENCODEA D9A D10A
Figure 1.
Rev. C
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved.
AD13280
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
Timing Diagram ........................................................................... 6
Absolute Maximum Ratings............................................................ 7
Explanation of Test Levels ........................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 12
Input and Output Stages................................................................ 13
Theory of Operation ...................................................................... 14
Using the Single-Ended Input .................................................. 14
Using the Differential Input...................................................... 14
Applications Information .............................................................. 15
Encoding the AD13280 ............................................................. 15
Jitter Consideration.................................................................... 15
Power Supplies ............................................................................ 16
Output Loading .......................................................................... 16
Evaluation Board ............................................................................ 17
Layout Information.................................................................... 17
Bill of Materials List for Evaluation Board.............................. 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 26
REVISION HISTORY
4/08—Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 25
Changes to the Ordering Guide.................................................... 26
11/05—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Features and Product Highlights ............................... 1
Changes to General Description .................................................... 3
Changes to Table 1............................................................................ 4
Changes to Figure 3.......................................................................... 8
Changes to Theory of Operation.................................................. 14
Changes to Equation 1 ................................................................... 15
Changes to Table 5.......................................................................... 18
Changes to Figure 21...................................................................... 19
Changes to Figure 22...................................................................... 20
Changes to Figure 23...................................................................... 21
Changes to Figure 28 and Figure 29............................................. 24
Updated Outline Dimensions ....................................................... 25
Changes to the Ordering Guide.................................................... 26
8/02—Rev. 0 to Rev. A
Edits to Specifications .......................................................................2
Packages Updated........................................................................... 19
Rev. C | Page 2 of 28
AD13280
GENERAL DESCRIPTION
The AD13280 is a complete, dual-channel, signal processing
solution that includes on-board amplifiers, references, ADCs, and
output termination components to provide optimized system
performance. The AD13280 has on-chip track-and-hold circuitry
and uses an innovative multipass architecture to achieve 12-bit, 80
MSPS performance. The AD13280 uses innovative high density
circuit design and laser-trimmed thin-film resistor networks to
achieve exceptional channel matching, impedance control, and
performance while maintaining excellent isolation and
providing for significant board area savings.
Multiple options are provided for driving the analog input,
including single-ended, differential, and optional series fil-
tering. The AD13280 also offers users a choice of analog input
signal ranges to further minimize additional external signal
conditioning, while remaining general purpose.
The AD13280 operates with ±5.0 V for the analog signal condi-
tioning with a separate 5.0 V supply for the analog-to-digital
conversion and 3.3 V digital supply for the output stage. Each
channel is completely independent, allowing operation with
independent encode and analog inputs and maintaining
minimal crosstalk and interference.
The AD13280 is available in a 68-lead, ceramic gull wing package.
The components are manufactured using the Analog Devices, Inc.,
high speed complementary bipolar process (XFCB).
Rev. C | Page 3 of 28
AD13280
SPECIFICATIONS
AV
CC
= +5 V, AV
EE
= −5 V, DV
CC
= +3.3 V; applies to each ADC with front-end amplifier, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY
1
No Missing Codes
Offset Error
Offset Error Channel Match
Gain Error
2
Gain Error Channel Match
Temperature
Test Level
Min
AD13280AZ
Typ
12
Guaranteed
±1.0
±1.0
±0.1
−1.0
±2.0
±0.5
±1.0
±1.0
Max
Unit
Bits
Full
25°C
Full
Full
25°C
Full
25°C
Max
Min
IV
I
VI
VI
I
VI
I
VI
VI
−2.2
−2.2
−1.0
−3
−5.0
−1.5
−3.0
−5
+2.2
+2.2
+1.0
+1
+5.0
+1.5
+3.0
+5
% FS
% FS
%
% FS
% FS
%
%
%
SINGLE-ENDED ANALOG INPUT
Input Voltage Range
AMP-IN-X-1
AMP-IN-X-2
Input Resistance
AMP-IN-X-1
AMP-IN-X-2
Capacitance
Analog Input Bandwidth
3
DIFFERENTIAL ANALOG INPUT
Analog Signal Input Range
A+IN to A–IN and B+IN to B−IN
4
Input Impedance
Analog Input Bandwidth
ENCODE INPUT (ENCODE, ENCODE)
1
Differential Input Voltage
Differential Input Resistance
Differential Input Capacitance
SWITCHING PERFORMANCE
Maximum Conversion Rate
5
Minimum Conversion Rate
5
Aperture Delay (t
A
)
Aperture Delay Matching
Aperture Uncertainty (Jitter)
ENCODE Pulse Width High at Max Conversion Rate
ENCODE Pulse Width Low at Max Conversion Rate
Output Delay (t
OD
)
Encode, Rising to Data Ready, Rising Delay
SNR
1, 6
Analog Input @ 10 MHz
Full
Full
Full
Full
25°C
Full
V
V
IV
IV
V
V
99
198
±0.5
±1.0
100
200
4.0
143
101
202
7.0
V
V
Ω
Ω
pF
MHz
Full
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
Full
25°C
Min
Max
25°C
Min
Max
V
V
V
IV
V
V
VI
IV
V
IV
V
IV
IV
V
V
I
II
II
I
II
II
0.4
±1
618
50
V
Ω
MHz
V p-p
kΩ
pF
MSPS
MSPS
ns
ps
ps rms
ns
ns
ns
ns
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
10
2.5
80
30
0.9
250
0.3
6.25
6.25
5
8.5
70
500
8
8
4.75
4.75
Analog Input @ 21 MHz
66.5
64.5
66.3
66.5
64
66.3
70
Rev. C | Page 4 of 28
AD13280
Parameter
Analog Input @ 37 MHz
Temperature
25°C
Min
Max
25°C
Min
Max
25°C
Min
Max
25°C
Min
Max
25°C
Min
Max
25°C
Min
Max
25°C
Min
Max
25°C
25°C
25°C
25°C
25°C
Min
Max
25°C
25°C
25°C
25°C
Test Level
I
II
II
I
II
II
I
II
II
I
II
II
I
II
II
I
II
II
I
II
II
V
V
V
V
I
II
II
V
V
IV
V
75
71
74
Min
63
61.5
63
66
63.5
66
64
63
64
54
53
54
75
70
75
68
67
67
56
55
55
AD13280AZ
Typ
65
Max
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
SINAD
1, 7
Analog Input @ 10 MHz
69
Analog Input @ 21 MHz
68.5
Analog Input @ 37 MHz
59
SPURIOUS-FREE DYNAMIC RANGE
1, 8
Analog Input @ 10 MHz
80
Analog Input @ 21 MHz
75
dBFS
Analog Input @ 37 MHz
62
dBFS
SINGLE-ENDED ANALOG INPUT
Pass-Band Ripple to 10 MHz
Pass-Band Ripple to 25 MHz
DIFFERENTIAL ANALOG INPUT
Pass-Band Ripple to 10 MHz
Pass-Band Ripple to 25 MHz
TWO-TONE IMD REJECTION
9
f
IN
= 9.1 MHz and 10.1 MHz (f
1
and f
2
are −7 dBFS)
0.07
0.12
0.3
0.82
80
dB
dB
dB
dB
dBc
f
IN
= 19.1 MHz and 20.7 MHz (f
1
and f
2
are −7 dBFS)
f
IN
= 36 MHz and 37 MHz (f
1
and f
2
are −7 dBFS)
CHANNEL-TO-CHANNEL ISOLATION
10
TRANSIENT RESPONSE
DIGITAL OUTPUTS
11
Logic Compatibility
DV
CC
= 3.3 V
Logic 1 Voltage
Logic 0 Voltage
DV
CC
= 5 V
Logic 1 Voltage
Logic 0 Voltage
Output Coding
POWER SUPPLY
AV
CC
Supply Voltage
12
I (AV
CC
) Current
AV
EE
Supply Voltage
12
I (AV
EE
) Current
DV
CC
Supply Voltage
12
77
60
90
25
CMOS
dBc
dBc
dB
ns
Full
Full
Full
Full
I
I
V
V
2.5
DV
CC
− 0.2
0.2
DV
CC
− 0.3
0.35
Twos complement
0.5
V
V
V
V
Full
Full
Full
Full
Full
Rev. C | Page 5 of 28
IV
I
IV
I
IV
4.85
−5.25
3.135
5.0
313
−5.0
38
3.3
5.25
364
−4.75
49
3.465
V
mA
V
mA
V
