ESMT
Features
16/18/20/24-bit input with I
2
S, Left-alignment
and Right-alignment data format
PSNR & DR(A-weighting)
Loudspeaker: 93dB (PSNR), 98dB (DR)
Headphone: 86dB (PSNR), 96dB (DR)
Multiple sampling frequencies (Fs)
32kHz / 44.1kHz / 48kHz and
64kHz / 88.2kHz / 96kHz
System clock = 64x,128x,192x,256x,384x,
512x, 576x, 768x, 1024x Fs
64x~1024x Fs for 32kHz / 44.1kHz / 48kHz
64x~512x Fs for 64kHz / 88.2kHz / 96kHz
Supply voltage
3.0~12V for loudspeaker driver
3.0~3.3V for others
Loudspeaker output power
2×10W(Full,8Ω) @ 1kHz and 10% THD+N
2×12.5W(Full,6Ω) @ 1kHz and 10% THD+N
2×16W(Full,4Ω) @ 1kHz and 10% THD+N
Headphone power
34mW into 32Ω@1kHz and 1% THD+N
65mW into 16Ω@1kHz and 1% THD+N
110mW into 8Ω@1kHz and 1% THD+N
200mW into 4Ω@1kHz and 1% THD+N
Sound processing including：
Bass (+18dB~-12dB, 3dB frequency is 250Hz),
Treble (+18dB~-12dB, 3dB frequency is 7kHz),
5 bands parametric EQ,
Volume control (+24dB~-103dB, 1dB/step) and
Dynamic range control
Anti-pop design
Over-temperature protection
Under-voltage shutdown
Short-circuit protection
I
2
C control interface
AD8256A
2x16W Stereo Digital Audio Amplifier with Headphone Driver
Applications
CD and DVD
TV audio
Car audio
Boom-box
MP3 docking systems
Portable / Handheld
Powered speaker
Wireless audio
USB speaker
Description
This is a stereo fully digital audio amplifier with
output power which can deliver up to 2×16W to 4Ω
load with 12V supply voltage. Using I
2
C digital
control interface, AD8256A provides sound
processing functions including Volume, Bass, Treble,
EQ, Mixing and Dynamic Range Control (DRC).
ORDERING INFORMATION
Product Number
AD8256A-KG
AD8256A-LEG
Package
7x7 48L QFN
7x7 48L E-LQFP
Comments
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.3
1/33
ESMT
Pin Assignment
AD8256A
MCLK
PLLGND
PLLVDD
CLK_OUT
DVDD
DGND2
DGND1
N.C.
SDATA0
SDATA1
SDATA2
LRCIN
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
HPL
HPR
AGND
AVDD
PWMSA
DEF
SDA
SCL
SA1
SA0
ERROR
PD
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
NAME
MCLK
PLLGND
PLLVDD
CLK_OUT
DVDD
DGND2
DGND1
N.C.
SDATA0
SDATA1
SDATA2
LRCIN
BCLK
VDDRB1
RB1
GNDR1
RA1
VDDRA1
VDDRA2
I
I
I
I
I
P
O
P
O
P
P
TYPE
DESCRIPTION
Master clock input
Ground for PLL
Supply for PLL
PLL output
Digital Power
Digital Ground2
Digital Ground1
No Connection
Serial audio data input 0
Serial audio data input 1
Serial audio data input 2
Left/Right clock input (Fs)
Bit clock input (64Fs)
Supply1 for right channel B
Right channel output1 (-)
Ground1 for right channel
Right channel output1 (+)
Supply1 for right channel A
Supply2 for right channel A
CHARACTERISTICS
Schmitt trigger TTL input buffer
I
P
P
O
P
P
P
(Note1)
TTL output buffer
(Note1)
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
(Note2)
(Note2)
(Note2)
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.3
2/33
ESMT
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
RA2
GNDR2
RB2
VDDRB2
Re set
PD
ERROR
AD8256A
O
P
O
P
I
I
O
I
I
I
I
I
O
P
P
O
O
I
P
O
P
O
P
P
O
P
O
P
I
Right channel output2 (+)
Ground2 for right channel
Right channel output2 (-)
Supply2 for right channel B
Reset, low active
Power down, low active
ERROR output
I
2
C select address 0
I
2
C select address 1
I
2
C serial clock input
I
2
C serial data input
Default volume, 0=Mute, 1=Un-Mute
Half-bridge, sub-woofer channel output
Analog supply
Analog ground
Headphone right channel output
Headphone left channel output
Headphone detection
Supply2 for left channel B
Left channel output2 (-)
Ground2 for left channel
Left channel output2 (+)
Supply2 for left channel A
Supply1 for left channel A
Left channel output1 (+)
Ground1 for left channel
Left channel output1 (-)
Supply1 for left channel B
PLL Bypass
(Note2)
Schmitt trigger TTL input buffer
(Note2)
(Note2)
(Note2)
(Note2)
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Open-drain output
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer with
open-drain output
Schmitt trigger TTL input buffer
TTL output buffer
(Note1)
SA0
SA1
SCL
SDA
DEF
PWMSA
AVDD
AGND
HPR
HPL
HP-SPK
VDDLB2
LB2
GNDL2
LA2
VDDLA2
VDDLA1
LA1
GNDL1
LB1
VDDLB1
PLL_Byp
Note1：These pins provide the supply for digital PWM controller, headphone drivers, built-in PLL and
protection circuits except for loudspeaker short-circuit protection circuits.
Note2：These pins provide the supply for loudspeaker driver stages, which are known as “PVDD”.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.3
3/33
ESMT
Functional Block Diagram
AD8256A
Available Package
Package Type
7x7 48L QFN
7x7 48L E-LQFP
Device No.
AD8256A
θ
ja
(℃/W)
23.5
23.8
Ψ
jt
(℃/W)
1.6
1.8
θ
jc
(℃/W)
12.5
15.8
Exposed Thermal Pad
Yes (Note3)
Note3：The thermal pad is at the bottom of package. To optimize the performance of thermal dissipation,
solder the thermal pad to PCB’s ground plane is suggested.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.3
4/33
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