Quick Start
DEMO9910HW Demonstration Board for ADC1207S080
Rev. 2.0 — 2 July 2012
Quick Start
Document information
Info
Keywords
Content
DEMO9910HW, PCB1337-1, Demonstration board, ADC, Converter,
ADC1207S080
This document describes how to use the demonstration board
DEMO9910HW for the analog-to-digital converter ADC1207S080.
Abstract
Overview
Revision history
Rev
2.0
0.1
Date
20120702
20080610
Description
Rebranded.
Initial version.
1. Quick start
1.1 Setup overview
Figure Fig 1
presents the connections to measure DEMO9910HW.
PULSE
GENERATOR
C
LOCK SIGNAL
(CLK)
. TTL/CMOS
S
YNCHRONIZED
P
RESENTED CONFIGURATION
. 2V
pp
input full scale
. Single TTL-CMOS clock signal
. Input common mode from IC
. Binary ADC output
. Medium CCS delay
LOGIC ANALYZER
SYNTHESIZED
SIGNAL
GENERATOR
I
NPUT SIGNAL
. 2V
pp
sinewave
. AC
F
ILTER
. High-order
. Band pass
P
OWER SUPPLY
. 5V
. I = 230 mA
.GND
Output data
. CCS for synchro
. DO (LSB) to D11 (MSB)
Fig 1. DEMO9910HW setup
1.2 Power supply
The board is powered with a single 5 V
DC
power supply. A power supply regulator is used
to supply all the 3.3 V circuitry on the board.
Table 1.
Name
J5
D2
TM1
TM2
TB1
TB2
General power supply
Function
+5V green connector – Power supply 5 V
DC
/ 230 mA.
PWR green light – It indicates the good supply plugging
DGND test point – Digital ground
AGND test point – Analog ground
+3V3 test point – Output stage power supply
+5V test point – ADC core power supply
View
1.3 Input signals (IN, CLK)
The input clock signal can be either a sinewave or a TTL-CMOS signal. The selection is
made with 2 soldered straps on the board.
To ensure a good evaluation of the device, the input signal and the input clock must be
synchronized together.
Moreover, the input frequency (Fi, MHz) and the clock frequency (Fclk, Msps) should
follow the formula:
,where M is an odd number of period and N is the number of samples.
Table 2.
Name
J3
J4
Input signals
Function
IN connector – Analog input signal (
50
matching)
CLK (TTL) connector – Single clock input signal (
50
matching)
CLK (SIN) connector – Clock input signal (
50
matching)
for differential sinewave drive.
Strap – Selection between J4 (single clock drive) or the
transformer (differential clock drive).
Strap – Selection between DGND (single clock drive) or
the transformer (differential clock drive).
View
J2
ST1
ST2
1.4 Output signals (D0 to D11, IR, CCS)
The digital output signal is available in binary or 2’s complement format.
A Complete Conversion Signal (CCS) is provided by the device for the datas acquisition
and its delay is referenced to the middle of the active data.
Table 3.
Name
J1
Output signals
Function
Array connector – ADC digital output(D0 to D11), In range
signal (IR) and Complete Conversion Signal (CCS)
IR green light – It indicates that the analog input signal is
in the full scale range
OTC switch – Output format selection
View
D1
S1
Binary
2’s complement
S2,S3
DEL0, DEL1 switches – CCS delay selection
DEL1
0
DEL0
CCS delay
Switches
0
High
impedance
0
1
0.3 ns
1
0
1.3 ns
1
1
2.3 ns
2. Example
2.1 Setup example
Hardware process
70 MHz
1.0 V
rms
8133A
H
EWLETT
P
ACKARD
3GHz pulse generator
Channel 1
70 Msps
0 to 3V
1.
Data acquisition
8644A
H
EWLETT
P
ACKARD
0.26-1030 MHz synthesized
signal generator
8644A
H
EWLETT
P
ACKARD
0.26-1030 MHz synthesized
signal generator
93 MHz
-0.5 dBFS
10 MH
Z
SYNCHRO
CCS
D0 to D11
8BP8 – 93/9.3
Bandpass filter
93 MHz
1.9 V
pp
5V / 230 mA
16500C
H
EWLETT
P
ACKARD
Logic analysis system
Pod 1
E3620A
H
EWLETT
P
ACKARD
Dual output DC power supply
GND
Fig 2. ADC1207S080 hardware setup
