AME, Inc.
ATTM01/ATTM02
1. General Description
The ATTM01/ATTM02 are precision remote diode tem-
perature sensors with a 2-wire System Management Bus
(SMBus) serial interface. The ATTM01/ATTM02 measure:
(1) Local temperature and (2) the temperature of a remote
diode based transistor from Computer Processor Unit
(CPU), Graphic Processor Unit (GPU) or other ASICs.
The ATTM01/ATTM02 provide two system alarms:
ALERT# and OVERT#.
(1) ALERT# event occurs when any temperature goes
outside the value that setup by preprogrammed HIGH and
LOW temperature limit registers.
(2) OVERT# event occurs when any temperature ex-
ceeds the OVERT# programmed limit.
ATTM02 has a different SMBus address to the ATTM01.
The SMBus address of the ATTM01 is 0x90 and ATTM02
is 0x94.
Processor Thermal Monitor
2. Features
l
Remote and Local Temperature Sensing.
l
±
Accuracy.
1℃
l
Programmable HIGH/LOW Alarm Temperature
Thresholds.
l
ALERT# Output Supports SMBus Protocol.
l
OVERT# Output Useful for System Shutdown.
l
SMBus-compatible interface.
l
SMBus timeout support.
l
Packages: SOP-8 and MSOP-8
3. Pin Configuration/ Top Side Mark
VDD
D+
D-
OVERT#
1
Product Name
XXXX
(Data code)
XXXXXXX_XX
(Lot NO_IID)
8
7
6
5
SMBCLK
SMBDATA
ALERT#
GND
2
3
4
Figure1. ATTM01/ATTM02 Pin Diagram (Top View)
Rev. B.01
1
AME, Inc.
ATTM01/ATTM02
※
Ordering Information
Part number
ATTM01
ATTM01G
ATTM01M
ATTM01MG
ATTM02
ATTM02G
ATTM02M
ATTM02MG
Processor Thermal Monitor
Package
SOP-8
SOP-8, Green
MSOP-8
MSOP-8, Green
SOP-8
SOP-8, Green
MSOP-8
MSOP-8, Green
SMBus address
0x90
0x90
0x90
0x90
0x94
0x94
0x94
0x94
Marking
TM01
TM01G
TM01M
TM01MG
TM02
TM02G
TM02M
TM02MG
4. Pin Description
Pin Type Description
OD - Open-drain output
IN - Input pin
AIN - Analog input.
I/OD - Bi-directional with open-drain output.
Pin No.
1
2
3
4
5
6
7
8
Pin Name
VDD
D+
D-
OVERT#
GND
ALERT#
SMBDATA
SMBCLK
I/O Type
Power
AIN
AIN
OD
Ground
OD
I/OD
IN
3.3V Power Input.
Function
Thermal diode anode Input
Thermal diode cathode Input.
Power supply shutdown control.
Ground pin.
SMBus alert (interrupt) Output.
SMBus bi-directional data line.
SMBus clock Input.
2
Rev. B.01
AME, Inc.
ATTM01/ATTM02
n
Typical Application
3.3Vsb
Processor Thermal Monitor
3.3V
C3
10u
VCORE
U2
4.7k
C6
R6
2.2n
4.7k
3
4
R4
0
ATTM01/ATTM02
1
2
VDD
D+
D
-
OVERT#
SMBCLK
SMBDATA
ALERT#
GND
8
7
6
5
SCLK
SDA
C4
47p
C5
47p
4.7k
C2
0.1u
C1
100p
R1
R2
South bridge
3.3V
Shutdown circuit
THERMTRIP#
CPU
R7
4.7k
Rev. B.01
3
AME, Inc.
ATTM01/ATTM02
6. Electrical Specifications
(These specifications apply for V
CC
= 3.3V and T
A
= +25
o
C, unless otherwise noted.) (Note 1)
Parameter
Supply Voltage
Temperature Resolution
V
CC
= 3.3V, T
A
=+25°C to +100°C,
V
CC
V
CC
T
RJ
= +60°C to +100°C
= 3.3V, T
A
=+25°C to +100°C,
T
RJ
= 0°C to +100°C
= 3.3V, T
A
=+25°C to +100°C,
T
RJ
= 0°C to +125°C
V
CC
= 3.3V,
Local Temperature Error
T
A
= +60°C to +100°C
V
CC
= 3.3V,
T
A
= 0°C to +100°C
Supply Sensitivity of Temperature Error
UVLO Hysteresis
UVLO Threshold
Power-On-Reset (POR) Threshold
Power-On-Reset (POR) Hysteresis
Standby Supply Current
Operating Current
Conversion Time
Conversion Time Error
Remote-Diode Source Current
ALERT, OVERT
Output Low Voltage
Output High Leakage Current
SMBus-COMPATIBLE INTERFACE (SMBCLK AND SMBDATA)
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Output Low-Sink Current
Input Capacitance
4
Processor Thermal Monitor
Symbol
V
CC
Test Conditions
Min
3
0.5
Typ
Max Units
3.6
V
°C
9
-1.0
-3.0
-5.0
-2.0
-3.0
±0.2
120
Falling edge
Rising edge
2.62
2.74
120
SMBus static
During conversion
t
CONV
From stop bit to conversion completion
95
-25
I
RJ
High level
Low level
75
7.5
100
10
7.8
0.53
125
156
+25
140
14
+ 1.0
+ 3.0
+ 5.0
2.0
3.0
Bits
°C
°C
°C
°C
°C
°C/V
mV
V
V
mV
µA
mA
ms
%
µA
Remote Temperature Error
I
SINK
= 1mA
I
SINK
= 4mA
V
OH
= 5.5V
0.4
0.6
1
V
V
µA
V
IL
V
IH
I
LEAK
I
SINK
C
IN
V
CC
= 3.0V
V
CC
= 5.5V
V
IN
= GND or V
CC
V
OL
= 0.6V
2.2
2.6
-1
6
5
0.8
V
V
V
1
µA
mA
pF
Rev. B.01
AME, Inc.
ATTM01/ATTM02
6. Electrical Specifications
Parameter
SMBus-COMPATIBLE TIMING
(Note 2)
Serial Clock Frequency
Bus Free Time Between STOP and
START Condition
START Condition Setup Time
Repeat START Condition Setup Time
START Condition Hold Time
STOP Condition Setup Time
Clock Low Period
Clock High Period
Data Setup Time
Receive SMBCLK/SMBDATA Rise Time
Receive SMBCLK/SMBDATA Fall Time
Pulse Width of Spike Suppressed
SMBus Timeout
t
SU:STA
t
HD:STA
t
SU:STO
t
LOW
t
HIGH
t
HD:DAT
t
R
t
F
t
SP
t
TIMEOUT
SMBDATA low period for interface reset
0
25
37
90% to 90%
10% of SMBDATA to 90% of SMBCLK
90% of SMBCLK to 90% of SMBDATA
10% to 10%
90% to 90%
(Note 4)
f
SMBCLK
t
BUF
(Note 3)
4.7
4.7
50
4
4
4.7
4
250
1
300
60
45
100
kHz
µs
µs
ns
µs
µs
µs
µs
µs
µs
ns
ns
ms
Symbol
Test Conditions
Min
Typ
Max Units
Processor Thermal Monitor
Note 1: All parameters tested at a single temperature. Specifications over temperature are guaranteed by design.
Note 2: Timing specifications guaranteed by design.
Note 3: The serial interface resets when SMBCLK is low for more than t
TIMEOUT
.
Note 4: A transition must internally provide at least a hold time to bridge the undefined region (300ns max) of
SMBCLK’s falling edge.
Rev. B.01
5
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