CCD 134
1024-Element
Linear Image Sensor
FEATURES
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1024 x 1 photosite array
13
µ
m x 13
µ
m photosites on 13µm pitch
µ
Anti-blooming and integration control
Enhanced spectral response (particularly in the
blue region)
Improved low-light performance over CCD133A
Low dark signal
High responsivity
High-speed operation
On-chip clock drivers
Dynamic range typical: 7500:1
Over 1V peak -to-peak outputs
Dark and white references contained in sample-
and -held outputs
Special selections available —consult factory
GENERAL DESCRIPTION
The CCD134 is a 1024-element line image sensor
designed for industrial measurement, telecine, and
document scanning applications which require high
resolution, high sensitivity and high data rate. The in-
corporation of on-chip antiblooming and integration
control allow the CCD134 to be extremely useful in an
industrial measurement and control environment or en-
vironments where lighting conditions are difficult to
control.
Fairchild Imaging, Inc.,
1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
CCD134
Fig. 1 BLOCK DIAGRAM
The CCD134 is similar to the CCD133A except for the additional
features of anti-blooming and integration control. The CCD134 is a
third generation device having an overall improved performance
compared with first and second generation devices, including en-
hanced blue response and excellent low light level performance.
The device incorporates on-chip clock driver circuitry and is capable
of high-speed operation up to a 20MHz data rate. The photoelement
size is 13µm (0.51 mils) x 13µm (0.51 mils) on 13µm (0.51 mils)
centers. The device is manufactured using Fairchild Weston ad-
vanced charge-coupled device n-channel isoplanar buried-channel
technology.
two registers serve to reduce peripheral electron noise in the inner
shift registers.
Two Gated Charge Detector/Amplifiers
— Charge packets
are transported to a precharged capacitor whose potential changes
linearly in response to the quantity of the signal charge delivered.
This potential is applied to the input gate of the two-stage NMOS
amplifiers producing a signal at the output “V
out
pins. The sample-
and-hold gate is a switching MOS transistor in the output amplifier
that allows the output to be delivered as a sample-and held wave-
form. The diode is recharged internally before the arrival of each new
signal charge-packet from the transport shift register.
FUNCTIONAL DESCRIPTION
The CCD134 consists of the following functional elements illustrated
in the Block Diagram and Circuit Diagram (Fig1.).
Integration and Anti-Blooming Control
— In many applica-
tions the dynamic range in parts of the image is larger than the dy-
namic range of the CCD, which may cause more electrons to be
generated in the photosite area than can be stored in the CCD shift
register. This is particularly common in industrial inspection and sat-
ellite applications. The excess electrons generated by bright illumi-
nation tend to “bloom” or “spill over” to neighboring pixels along the
shift register, thus “smearing” the information. This smearing can be
eliminated using two methods:
Photosites
— A row of 1024 image sensor elements separated
by a diffused channel stop and covered by a silicon dioxide surface
passivation layer. Image photons pass through the transparent sili-
con creating hole-electron pairs. The photon generated electrons
are accumulated in the photosites. The amount of charge accumu-
lated in each photosite is a linear function of the incident illumination
intensity and the integration period. The output signal will vary in an
analog manner from a thermally generated background level at zero
illumination to a maximum at saturation under bright illumination.
Anti-Blooming Operation:
A DC voltage applied to the integration control gate (approximately 5
to 7 volts) will cause excess charge generated in the photosites to be
diverted to the anti-blooming sink (V
SINK
) instead of the shift regis-
ters. This acts as a “clipping circuit” for the CCD output (see Fig. 2)
Transfer Gates
— This gate is a structure adjacent to the row of
image sensor elements. The charge packets accumulated in the
photosites are transferred in parallel via the transfer gate to the trans-
port shift registers whenever the transfer gate voltage goes high.
Alternate charge packets are transferred to the A and B transport
registers.
Integration Control Operation:
Variable integration times which are less than the CCD exposure time
may be attained by supplying a clock to the integration control gate.
Clocking
φ
IC
reduces the photosite signal in all photosites by the ra-
tion
t
EXPOSURE
/
t
INT
. Greater than 10:1 reduction in the average
photosite signal can be achieved with integration control.
The integration-control and anti-blooming features can be imple-
mented simultaneously. This is done by setting the
φ
IC
clock-low
level to approximately 5 to 7 volts.
Four 529 Bit Analog Transport Shift Registers
— Two reg-
isters are on each side of the line of image sensor elements and are
separated from it by the transfer gate. The two inside registers,
called the transport shift registers are used to move the light gener-
ated charge packets delivered by the transfer gates serially to the
charge detector amplifier. The complementary phase relationship
of the last elements of the two transport registers provides for alter-
nate delivery of charge packets at the output amplifiers. The outer
2
Fairchild Imaging, Inc.,
1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
CCD134
Fig. 2 INTEGRATION-CONTROL TIMING DIAGRAM AND NOTES
Fig. 3 TEST LOAD CONFIGURATION (INTERNAL SAMPLE-AND-HOLD ENABLED)
Fig. 4 TEST LOAD CONFIGURATION
(INTERNAL SAMPLE-AND-HOLD DISABLED)
Fig. 5 MAXIMUM OUTPUT VOLTAGE vs.
φ
IC
VOLTAGE
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Fairchild Imaging, Inc.,
1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
CCD134
PACKAGE OUTLINE
24- Pin Dual In-Line Ceramic Package
DEFINITION OF TERM
Charge-Coupled Device
—
A Charge-coupled device is a semi-
conductor device in which finite isolated charge-packets are trans-
ported from one position in the semiconductor to an adjacent posi-
tion by sequential clocking of an array of gates. The charge-packets
are minority carriers with respect to the semiconductor substrate.
Total Photoresponse Non-Uniformity
- The difference of the
response levels of the most and the least sensitive element under
uniform illumination. Measurement of PRNU excludes first and last
elements.
Dark Signal
- The output signal in the dark caused by thermally
generated electrons that is a linear function of the integration time
and is highly sensitive to temperature.
Sample-and Hold Clock
(φ
SHCA
,
φ
SHCB
) - The voltage wave form
for triggering the sample-and-hold gates in the output amplifiers to
create a continuous sampled video signal at the output. The sample-
and-hold feature may be defeated by connecting
φ
SHCA
and
φ
SHCB
to
V
DD
. Use of the internal sample-and-hold capability is possible for
data rates upt to 13MHz. For use above 13MHz consult factory.
Saturation Output Voltage
- The maximum usable signal out-
put voltage. Charge transfer efficiency decreases sharply when the
saturation output voltage is exceeded.
Integration Time
- The time interval between the falling edge of
the integration control clock and the falling edge of the transfer clock.
The integration time is the time in which charge is accumulated in
the photosites.
Dark Reference
— Video output level generated from sensing
elements covered with opague metalization which provides a refer-
ence voltage equivalent to device operation in the dark. This per-
mits use of external DC restoration circuitry.
Exposure Time
- The time interval between the falling edge of the
two transfer pulses (φ
X
) as shown in the timing diagram. The expo-
sure time is the time between transfers of signal charge from the
photosites into the transport registers.
Isolation Cell
— This is a site on-chip producing an element in the
video output that serves as a buffer between valid video data and
dark reference signals. The output from an isolation cell contains
no valid information and should be ignored.
Pixel
- A picture element (photosite).
Dynamic Range
— The saturation exposure divided by the RMS
temporal noise equivalent exposure., Dynamic range is sometimes
defined in terms of peak-to-peak noise. To compare the two defini-
tions a factor of four to six is generally appropriate in that peak-to-
peak noise is approximately equal to four to six times RMS noise.
RMS Noise Equivalent Exposure
— The exposure level that
gives an output signal equal to the RMS noise level at the output in
the dark.
Saturation Exposures
— The minimum exposure level that will
provide a saturation output signal. Exposure is equal to the light
intensity times the photosite integration time.
Charge Transfer Efficiency
— Percentage of valid charge in-
formation that is transferred between each successive stage of the
transport registers.
Responsivity
— The output signal voltage per unit exposure for a
specified spectral type of radiation. Responsivity equals output volt-
age divided by exposure.
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Fairchild Imaging, Inc.,
1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
CCD134
5
Fairchild Imaging, Inc.,
1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
嵌入式系统
