CCD42-90 Back Illuminated
High Performance CCD Sensor
FEATURES
*
*
*
*
*
*
*
*
*
*
2048 by 4608 Pixel Format
13.5
mm
Square Pixels
Image Area 27.6 x 62.2 mm
Back Illuminated Format for High Quantum Efficiency
Low Noise Output Amplifiers
Wide Dynamic Range
Symmetrical Anti-static Gate Protection
3-side Buttable Package
Gated Dump Drain on Readout Register
Flatness better than 15
mm
peak to valley
APPLICATIONS
*
*
TYPICAL PERFORMANCE (at 173 K)
Pixel readout frequency .
Output amplifier sensitivity
Peak signal . . . . .
Spectral range . . . .
Readout noise (at 20 kHz)
QE at 500 nm . . . .
Charge transfer efficiency
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 20 –
. . .
. . .
200 –
. . .
. . .
. . .
3000
kHz
. 4.5
mV/e
7
150 ke
7
/pixel
1060
nm
7
. 3
e rms
90
%
99.9995
%
Astronomy
Scientific Imaging
INTRODUCTION
This version of the CCD42 family of CCD sensors has full-frame
architecture. Back illumination technology, in combination with
an extremely low noise amplifier, makes the device well suited
to the most demanding applications, such as astronomy.
The output amplifier is designed to give excellent noise levels at
low pixel rates and can match the noise performance of most
conventional scientific CCDs at pixel rates as high as 1 MHz.
The low output impedance and optional FET buffer simplify the
interface with external electronics.
The readout register has a gate controlled dump-drain to allow
fast dumping of unwanted data. The register is designed to
accommodate four image pixels of charge and a summing well
is provided capable of holding six image pixels. The output
amplifier has a feature to enable the responsivity to be reduced,
allowing the reading of such large charge packets.
The device is supplied in a package designed to facilitate the
construction of large close-butted mosaics and is designed to
be used cryogenically. The design of the package will ensure
that the device flatness is maintained at the working
temperature.
The sensor is shipped in a protective container, but no
permanent window is fitted.
GENERAL DATA
Format
Image area . . . . . . . .
Active pixels (H) . . . . . .
(V)
. . . . . .
Pixel size . . . . . . . . .
Number of output amplifiers
. .
Number of underscan (serial) pixels
The device has a 100% fill factor.
. 27.6 x 62.2
. .
2048
. 4608 + 4
. 13.5 x 13.5
. . . . 2
. . .
50
mm
mm
Package
Format . . . .
invar metal
Focal plane height above base .
Package size . . . . . . .
Package weight . . . . . .
Number of pins . . . . . .
Inactive edge spacing:
sides . . . . . . . . .
top . . . . . . . . .
bottom (edge connections) .
package with PGA connector
. . . .
14.0
mm
. . 28.2 x 67.3
mm
. . . . 150
g approx
. . . .
40
. . 260
+
50
. . 120
+
50
. . . . . 5.0
mm
mm
mm
e2v technologies (uk) limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU, UK Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492
e-mail: enquiries@e2v.com Internet: www.e2v.com
Holding Company: e2v technologies plc
e2v technologies inc. 4 Westchester Plaza, PO Box 1482, Elmsford, NY10523-1482 USA Telephone: (914) 592-6050 Facsimile: (914) 592-5148
e-mail: enquiries@e2vtechnologies-na.com
#
e2v technologies (uk) limited 2006
A1A-100026 Issue 8, March 2006
411/9572
PERFORMANCE (at 173 K unless stated)
Min
Peak charge storage (see note 1)
Peak output voltage (unbinned)
Dark signal at 153 K (see note 2)
Charge transfer efficiency (see note 3):
parallel
serial
Output amplifier sensitivity (see note 4)
Readout noise (see note 5)
Readout frequency (see note 6)
Output node capacity (see note 4):
OG2 low (mode 1)
OG2 high (mode 2)
Serial register capacity
99.999
99.999
3.0
–
–
–
–
–
100k
Typical
150k
675
50.1
99.9995
99.9995
4.5
3
20
200k
1000k
600k
6.0
4
3000
–
–
–
1
7
Max
-
e
7
/pixel
mV
e /pixel/hour
%
%
mV/e
7
rms e
7
/pixel
kHz
electrons
electrons
e
7
/pixel
Spectral Response at 173 K (Astronomy broadband devices)
Spectral Response (QE)
Wavelength (nm)
350
400
500
650
900
Typical
50
80
90
80
30
Min
40
70
80
75
25
Response
Non-uniformity, max (1s)
–
3
–
3
5
%
%
%
%
%
Note
Devices with alternate spectral response are also available.
ELECTRICAL INTERFACE CHARACTERISTICS
Electrode capacitances (measured at mid-clock level)
Min
I1/I1 interphase
R1/R1 interphase
I1/SS
R1/SS
Output impedance
–
–
–
–
–
Typical
35
80
70
150
350
Max
–
–
–
–
–
nF
pF
nF
pF
O
NOTES
1. Signal level at which resolution begins to degrade.
2. Dark signal is typically measured at 188 K and V
ss
= +9 V.
The dark signal at other temperatures may be estimated
from:
Q
d
/Q
d0
= 122T
3
e
76400/T
where Q
d0
is the dark current at 293 K.
3. Measurements made using charge generated by X-ray
photons of known energy. Charge transfer efficiency is
measured for a complete three-phase triplet.
4. Operation of the OG2 gate modifies the output node. OG2
= LO (mode 1) is normally used for low noise, high
responsivity. See also note 9.
5. Measured using a dual-slope integrator technique (i.e.
correlated double sampling) with a 10
ms
integration period
with OG2 = OG1 + 1 V.
6. Readout above 3000 kHz can be achieved but performance
to the parameters given cannot be guaranteed.
100026, page 2
#
e2v technologies
TYPICAL SPECTRAL RESPONSE
(At
790 8C,
measured with astronomy broadband AR coating)
100
7640A
90
80
70
60
50
40
30
QUANTUM EFFICIENCY (%)
20
10
0
300
400
500
600
700
800
900
1000
1100
WAVELENGTH (nm)
TYPICAL OUTPUT CIRCUIT NOISE
(Measured using clamp and sample, temperature range 140 - 230 K)
15
7639
NOISE EQUIVALENT SIGNAL (e
—
rms)
10
5
0
10k
FREQUENCY (Hz)
50k
100k
500k
1M
5M
#
e2v technologies
100026, page 3
BLEMISH SPECIFICATION
Pixels where charge is temporarily held.
Traps are counted if they have a capacity
greater than 200 e
7
at 173 K.
Slipped columns
Are counted if they have an amplitude
greater than 200 e
7
.
Black spots
Are counted when they have a responsivity
of less than 80% of the local mean signal.
White spots
Are counted when they have a generation
rate equivalent to 100 electrons per pixel
per hour at 153 K (typically measured at
188 K). The typical temperature depen-
dence of white spot blemishes is the same
as that of the average dark signal, i.e.:
Q
d
/Q
d0
= 122T
3
e
76400/T
Column defects
A column which contains at least 100 white
or black defects.
Traps
GRADE
Column defects
(black or white)
White spots
Traps
Total spots
(black and white)
GRADE 5
0
2
300
15
900
1
6
450
30
1350
2
12
800
50
2000
3
24
1200
75
3000
Devices which are fully functional, with
image quality below that of grade 3, and
which may not meet all other performance
parameters; not all parameters may be
tested.
CLOCK ARCHITECTURE
7896
1
1
nth line
2
2
3
1024th column – right section
1st column – right section
1
3
Fourth line
1
Third line
2
3
1
2
3
1
2
3
1
Parallel transfer phases
Second line
2
3
1
First line
2
3
2 1 3 2 1 3 2 1 3 1 2 3 1 2 3 1 2
Serial transfer phases
3 1 2
OSR
OG2R
OG1R
1SWR
1SWL
OG1L
OG2L
OSL
3 1 2 3 1
50 elements
2 1 3
2
3
50 elements
R12R
R11R
R13
R11L
R12L
100026, page 4
#
e2v technologies
CONNECTIONS, TYPICAL VOLTAGES AND ABSOLUTE MAXIMUM RATINGS
40-pin PGA connector
CLOCK
PGA
PIN
A1, A8,
C1, C8,
F2, F7
D8
E8
F8
D4
E4
D5
E5
F6
E3
E6
E2
E7
F3
D3
D6
B2
B7
D2
D7
B1
B8
A2
A7
C2
C7
A3
A6
B3
B6
C3
C6
D1, F1
E1
REF
V
SS
DESCRIPTION
Substrate
LOW
Typical
n/a
Min
0
CLOCK HIGH OR
DC LEVEL (V)
Typical
9
Max
10
MAXIMUM RATINGS
with respect to V
SS
–
I11
I12
I13
R11(L)
R12(L)
R11(R)
R12(R)
R13
1R(L)
1R(R)
1SW(L)
DG
OG1(L)
OG1(R)
DD(L)
DD(R)
OG2(L)
OG2(R)
OD(L)
OD(R)
OS(L)
OS(R)
RD(L)
RD(R)
RL(L)
RL(R)
OP(L)
OP(R)
JD(L)
JD(R)
Temp
–
Image area clock, phase 1
Image area clock, phase 2
Image area clock, phase 3
Register clock phase 1 (left)
Register clock phase 2 (left)
Register clock phase 1 (right) (see note 7)
Register clock phase 2 (right) (see note 7)
Register clock phase 3
Reset gate (left)
Reset gate (right)
Summing well gate (left)
Dump gate (see note 8)
Output gate 1 (left)
Output gate 1 (right)
Dump drain (left)
Dump drain (right)
Output gate 2 (left) (see note 9)
Output gate 2 (right) (see note 9)
Output drain (left)
Output drain (right)
Output source (left)
Output source (right)
Reset drain (left)
Reset drain (right)
Load resistor (left)
Load resistor (right)
JFET source (left)
JFET source (right)
JFET drain (left)
JFET drain (right)
Temperature sensor
No connection
0
0
0
1
1
1
1
1
0
0
0
0
0
n/a
n/a
n/a
n/a
4
4
n/a
n/a
n/a
n/a
n/a
n/a
8
8
8
9
9
9
9
9
9
9
9
9
–
2
2
20
20
16
16
27
27
10
10
10
11
11
11
11
11
12
12
11
11
12
3
3
24
24
20
20
29
29
see note 10
see note 10
15
15
15
15
15
15
15
15
15
15
15
15
15
4
4
26
26
24
24
–
–
+20
V
+20
V
+20
V
+20
V
+20
V
+20
V
+20
V
+20
V
+20
V
+20
V
+20
V
+20
V
+20
V
+20
V
+20
V
70.3
to +30 V
70.3
to +30 V
+20
V
+20
V
70.3
to +35 V
70.3
to +35 V
70.3
to +25 V
70.3
to +25 V
1SW(R)
Summing well gate (right)
15
15
17
17
A
GND
(0 V)
A
GND
(0 V)
see note 11
see note 11
OD(L) +2 V
OD(L) +2 V
Thermistor
–
–
–
70.3
to +25 V
70.3
to +25 V
Optional connections for 309 JFET
Other connections (options)
If all voltages are set to the typical values operation at, or close to, specification should be obtained. Some adjustment within the
minimum - maximum range specified may be required to optimise performance. Refer to the specific device test data if possible.
Maximum voltage between pairs of pins: OS to OD
+15
V.
Maximum current through any source or drain pin: 10 mA.
The CCD is not electrically connected to the metal package.
#
e2v technologies
100026, page 5
