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CCD42-90-0-B40

CCD Sensor

器件类别:传感器    传感器/换能器   

厂商名称:e2v technologies

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参数名称
属性值
厂商名称
e2v technologies
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compliant
传感器/换能器类型
IMAGE SENSOR,CCD
Base Number Matches
1
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CCD42-90 Scientific CCD Sensor
Back-illuminated, 2048 x 4612 Pixels,
Non Inverted Mode Operation
INTRODUCTION
The CCD42-90 is a large area full-frame (FF) imaging
device. Back illumination technology, in combination with an
extremely low noise amplifier, makes the devices well suited
to the most demanding astronomical and scientific imaging
applications.
DESCRIPTION
The device has an image area with 2048 x 4612 pixels each
13.5 µm square. There is a single read-out register with low-
noise amplifiers at both ends. Additional JFET buffers are
included in the package to provide an increased capability to
drive high-capacitance loads. A gate-controlled dump-drain
is provided to allow fast dumping of unwanted data. The
register is designed to accommodate four image pixels of
charge and a summing well is provided capable of holding
that from six image pixels. The output amplifier has a
feature to enable the responsivity to be reduced, allowing
the reading of such large charge packets.
The device is supplied in a package designed to facilitate
the construction of large close-butted mosaics used at
cryogenic temperatures. The design of the package will
ensure that the device flatness is maintained at the working
temperature.
The sensor is shipped in a protective container, but no
permanent window is fitted.
SUMMARY PERFORMANCE
(Typical values)
Number of pixels
Pixel size
Image area
Outputs
Package size
Package format
Focal plane height, above base
Connectors
Flatness
Amplifier responsivity
Readout noise (rms)
Maximum data rate
Image pixel charge storage
Dark signal at 173K
2048(H) x 4612(V)
13.5 µm square
27.6 mm x 62.2 mm
2
28.2mm x 67.3 mm
Invar metal package with
PGA connector
14.00 mm
PGA; 40 pins
15 µm p-v maximum
4.5 µV/e
3 e
at 20 kHz
3 MHz
150,000 e
3 e
/pixel/hour
VARIANTS
Standard silicon and deep depletion silicon device types can
be supplied with a range of AR coatings. Graded coatings
are available as custom variants.
Mating ZIF sockets are available to order.
PART REFERENCES
CCD42-90-g-xxx
g = cosmetic grade
xxx = device-specific part number
Details are given on the last page.
Devices with other formats (e.g. 2048 x 2048, 4096 x 4096
pixels) are also available in the same family.
Consult e2v technologies for further information on any of
the above options.
Quoted performance parameters given here are “typical”
values. Specification limits are shown later in this data
sheet.
Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof
and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond the set out in its standard conditions of sale in
respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein.
e2v technologies limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU United Kingdom Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492
e-mail:
enquiries@e2v.com
Internet:
www.e2v.com
Holding Company: e2v technologies plc
e2v technologies inc. 4 Westchester Plaza, PO Box 1482, Elmsford, NY10523-1482 USA Telephone: (914) 592-6050 Facsimile: (914) 592-5148 e-mail: enquiries@e2vtechnologies.us
© e2v technologies (uk) limited 2014
A1A-100026, Version 9, December 2014
118717
PERFORMANCE at 173 K
Electro-Optical Specification (Note 1)
Min
Peak charge storage (image)
Peak charge storage (register)
Output node capacity:
OG2 low (mode 1)
OG2 high (mode 2)
Typical
150k
600k
300k
1,200k
4.5
1.5
3
1
6
Max
-
-
-
-
Units
e
/pixel
e
/pixel
e
e
µV/e
Note
2a
2b
2c
100k
-
-
-
3.0
-
-
-
-
-
99.999
99.999
Output amplifier responsivity:
OG2 low (mode 1)
OG2 high (mode 2)
3
4
5
6
Read-out noise (mode 1)
Maximum read-out frequency
Dark signal
Specified at 173K
-
4
3
182
[1]
-
-
e
rms
MHz
e
/pixel/h
[Equivalent 153K value]
Charge transfer efficiency:
parallel
serial
99.9995
99.9998
%
%
7
NOTES
1.
Device performance will be within the limits specified by “max” and “min” when operated at the recommended voltages
supplied with the test data and when measured at a register clock frequency in the range 0.1 – 1.0 MHz. Most tests are
performed at a nominal 500 kHz pixel rate. The noise as specified is separately measured in accordance with note 4.
(a) Signal level at which resolution begins to degrade.
(b) Maximum register capacity.
(c) Output node capacity under different modes.
2.
3.
For highest responsivity and lowest nose (mode 1), the voltage on OG2 should be 1V higher than that on OG1. For
increased charge handling capacity, but with higher noise (mode 2), the voltage on OG1 should stay the same but the
voltage on OG2 should be taken to about 20V.
Measured at OS with correlated double sampling at 20 kHz pixel rate in mode 1.
Depending on the external load capacitance to be driven. Higher loads (> 20 pF) can benefit from use of the optional JFET
buffer. The register will transfer charge at higher frequencies, but performance cannot be guaranteed.
The dark signal is typically measured at a device temperature of 173K It is a strong function of temperature and the typical
average (background) dark signal is taken as:
Q
d
/Q
do
= 122T³e
-6400 /T
4.
5.
6.
where Q
do
is the dark current at 293 K.
Note that this is typical performance and some variation may be seen between devices. Dark current is lowest with the
substrate voltage at +9 V, and somewhat higher with substrate at 0 V. However, Vss=0V is now recommended for highest
spatial resolution; see note 9 later.
7.
Measured with a
55
Fe X-ray source. The CTE value is quoted for the complete clock cycle (i.e. not per phase).
© e2v technologies (uk) limited 2014
Document subject to disclaimer on page 1
A1A-100026 Version 9, page 2
COSMETIC SPECIFICATIONS
Maximum allowed defect levels are indicated below.
Standard silicon
Grade
Column defects (black or white)
White spots
Total spots (black and white)
Traps > 200 e-
0
2
300
900
15
1
6
450
1350
30
2
12
800
2000
50
Deep-depleted silicon
0
2
500
1500
15
1
6
1000
2000
30
2
12
1500
2500
50
Grade 5
devices may also be available for set-up purposes. These are fully functional but with an image quality
below that of grade 2, and may not meet all other specifications. Not all parameters may be tested.
DEFINITIONS
White spots
A defect is counted as a white spot if the dark generation rate is
5 e /pixel/s at 173 K.
-
(which is also equivalent to
≥100
e /hour at 153 K).
The temperature dependence is the same as for the mean dark signal; see note 6 above.
-
Black spots
Column defects
Traps
Defect exclusion zone
A black spot defect is a pixel with a photo-response less than 50% of the local mean.
A column is counted as a defect if it contains at least 100 white or dark single pixel defects.
A trap causes charge to be temporarily held in a pixel and these are counted as defects if
-
the quantity of trapped charge is greater than 200 e
Defect measurements are excluded from the outer two rows and columns of the sensor.
TYPICAL OUTPUT AMPLIFIER NOISE
The variation of typical read noise with operating frequency is shown below. This is measured using correlated double sampling
with a pre-sampling bandwidth equal to twice the pixel rate in mode 1, temperature range 150 – 230 K.
© e2v technologies (uk) limited 2014
Document subject to disclaimer on page 1
A1A-100026 Version 9, page 3
SPECTRAL RESPONSE
The table below gives guaranteed minimum values of the spectral response for several variants. PRNU is also shown.
Standard
silicon
Astro
Broadband
Wavelength
(nm)
350
400
500
650
900
Minimum
QE (%)
40
70
80
75
25
Standard
silicon
Astro
Midband
Minimum
QE (%)
20
50
80
80
25
Standard
silicon
Astro
Multi-2
Minimum
QE (%)
30
75
75
80
25
Deep
depletion
silicon
Astro
Broadband
Minimum
QE (%)
40
70
75
70
40
Deep
depletion
silicon
Astro
Midband
Minimum
QE (%)
20
50
80
80
40
Deep
depletion
silicon
Astro ER1
response
Minimum
QE (%)
20
35
65
80
45
Deep
depletion
silicon
Astro
Multi-2
Minimum
QE (%)
30
75
75
80
50
-
3
-
3
5
Maximum Pixel
Response
Non-
Uniformity
PRNU (1 σ) (%)
See also the figures below. Consult e2v technologies for availability of spectral response variants. Devices with alternate
spectral responses may be available to special order.
© e2v technologies (uk) limited 2014
Document subject to disclaimer on page 1
A1A-100026 Version 9, page 4
DEVICE ARCHITECTURE and ARRANGEMENT OF ELECTRODES
The device has a three-phase image area with a total of 2048(H) x 4612(V) pixels with connections IØ1, IØ2 and IØ3. The
three-phase read-out register is of split configuration with connections RØ1L, RØ1R, RØ2L, RØ2R and RØ3. Adjacent to the
register is a dump gate and drain structure with connections DG and DD, respectively. This may be used to dump unwanted
lines of charges as they are transferred from the image section. At either end of the register are an additional 50 elements
leading to the charge detection amplifiers. The last clocked electrodes are separately connected and designated ØSWL and
ØSWR – these may be used for summing well purposes or simply clocked as RØ3.
The parallel to serial transfer is with the RØ1 and RØ2 phases held at clock ‘high’. With the register connections as designated,
a line of charges will be split between the two outputs. To transfer a whole line to the left-hand amplifier the connections to
RØ1R and RØ2R should be transposed. To transfer a whole line to the right hand amplifier the connections to RØ1L and RØ2L
should be transposed.
© e2v technologies (uk) limited 2014
Document subject to disclaimer on page 1
A1A-100026 Version 9, page 5
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