CY14B101Q1
CY14B101Q2
CY14B101Q3
1 Mbit (128 K x 8) Serial SPI nvSRAM
Features
■
1-Mbit nonvolatile static random access memory (nvSRAM)
❐
Internally organized as 128 K × 8
❐
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (Hardware STORE) or SPI instruction (Software
STORE)
❐
RECALL to SRAM initiated on power-up
(Power-Up RECALL) or by SPI instruction
(Software RECALL)
❐
Automatic STORE on power-down with a small capacitor
(except for CY14B101Q1)
High reliability
❐
Infinite read, write, and RECALL cycles
❐
1 million STORE cycles to QuantumTrap
❐
Data retention: 20 years
High speed serial peripheral interface (SPI)
❐
40 MHz clock rate
❐
Supports SPI mode 0 (0,0) and mode 3 (1,1)
Write protection
❐
Hardware protection using Write Protect (WP) pin
❐
Software protection using Write Disable instruction
❐
Software block protection for 1/4,1/2, or entire array
Low power consumption
❐
Single 3 V +20%, –10% operation
❐
Average active current of 10 mA at 40 MHz operation
Industry standard configurations
❐
Industrial temperature
❐
CY14B101Q1 has identical pin configuration to industry
standard 8-pin NV memory
8-pin dual flat no-lead (DFN) package and 16-pin small
outline integrated circuit (SOIC) package
❐
Restriction of hazardous substances (RoHS) compliant
❐
Functional Overview
The
Cypress
CY14B101Q1/CY14B101Q2/CY14B101Q3
combines a 1 Mbit nvSRAM with a nonvolatile element in each
memory cell with serial SPI interface. The memory is organized
as 128 K words of 8 bits each. The embedded nonvolatile
elements incorporate the QuantumTrap technology, creating the
world’s most reliable nonvolatile memory. The SRAM provides
infinite read and write cycles, while the QuantumTrap cell
provides highly reliable nonvolatile storage of data. Data
transfers from SRAM to the nonvolatile elements (STORE
operation) takes place automatically at power-down (except for
CY14B101Q1). On power-up, data is restored to the SRAM from
the nonvolatile memory (RECALL operation). Both STORE and
RECALL operations can also be initiated by the user through SPI
instruction.
■
■
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14B101Q1
No
Yes
No
CY14B101Q2
Yes
Yes
No
CY14B101Q3
Yes
Yes
Yes
■
■
■
Logic Block Diagram
V
CC
V
CAP
CS
WP
SCK
HOLD
Instruction decode
Write protect
Control logic
QuantumTrap
128 K X 8
Power Control
SRAM Array
128 K X 8
STORE
RECALL
STORE/RECALL
Control
HSB
Instruction
register
D0-D7
Address
Decoder
A0-A16
SI
Data I/O register
SO
Status Register
Cypress Semiconductor Corporation
Document #: 001-50091 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 18, 2011
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CY14B101Q1
CY14B101Q2
CY14B101Q3
Contents
Pinouts .............................................................................. 3
Device Operation .............................................................. 4
SRAM Write................................................................. 4
SRAM Read ................................................................ 4
STORE Operation ....................................................... 4
AutoStore Operation .................................................... 5
Software STORE Operation ........................................ 5
Hardware STORE and HSB Pin Operation ................. 5
RECALL Operation...................................................... 5
Hardware RECALL (Power-Up) .................................. 5
Software RECALL ........................................................ 5
Disabling and Enabling AutoStore............................... 6
Noise Considerations ....................................................... 6
Serial Peripheral Interface ............................................... 6
SPI Overview............................................................... 6
SPI Modes................................................................... 7
SPI Operating Features .................................................... 8
Power-Up .................................................................... 8
Power On Reset .......................................................... 8
Power-Down ................................................................ 8
Active Power and Standby Power Modes ................... 8
SPI Functional Description .............................................. 8
Status Register ................................................................. 9
Read Status Register (RDSR) Instruction ................... 9
Write Status Register (WRSR) Instruction .................. 9
Write Protection and Block Protection ......................... 10
Write Enable (WREN) Instruction .............................. 10
Write Disable (WRDI) Instruction .............................. 10
Block Protection ........................................................ 10
Write Protect (WP) Pin .............................................. 11
Memory Access .............................................................. 11
Read Sequence (READ) instruction .......................... 11
Write Sequence (WRITE) instruction ........................ 11
Software STORE (STORE) instruction ...................... 13
Software RECALL (RECALL) instruction .................. 13
AutoStore Enable (ASENB) instruction ..................... 13
AutoStore Disable (ASDISB) instruction ................... 13
HOLD Pin Operation ................................................. 14
Best Practices ................................................................. 14
Maximum Ratings........................................................... 15
DC Electrical Characteristics ........................................ 15
Data Retention and Endurance ..................................... 16
Capacitance .................................................................... 16
Thermal Resistance........................................................ 16
AC Test Conditions ........................................................ 16
AC Switching Characteristics ....................................... 17
AutoStore or Power-Up RECALL .................................. 18
Software Controlled STORE and RECALL Cycles ...... 19
Hardware STORE Cycle ................................................. 20
Ordering Information ...................................................... 21
Ordering Code Definition ........................................... 21
Package Diagrams........................................................... 22
Acronyms ........................................................................ 24
Document Conventions ................................................. 24
Units of Measure ....................................................... 24
Document History Page ................................................ 25
Sales, Solutions, and Legal Information ...................... 26
Worldwide Sales and Design Support ....................... 26
Products .................................................................... 26
PSoC Solutions ......................................................... 26
Document #: 001-50091 Rev. *H
Page 2 of 26
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CY14B101Q1
CY14B101Q2
CY14B101Q3
Pinouts
Figure 1. Pin Diagram - 8-Pin DFN
[1, 2, 3]
CY14B101Q1
CS
SO
WP
VSS
O
CY14B101Q2
8
7
VCC
HOLD
SCK
SI
CS
O
1
2
3
4
Top View
(not to scale)
EXPOSED
PAD
1
2
3
4
Top View
(not to scale)
EXPOSED
PAD
8
7
6
5
VCC
HOLD
SCK
SI
SO
VCAP
VSS
6
5
Figure 2. Pin Diagram - 16-Pin SOIC
NC
1
2
3
4
5
6
7
8
CY14B101Q3
Top View
not to scale
16
15
14
13
12
11
10
9
V
CC
NC
V
CAP
SO
SI
SCK
CS
HSB
NC
NC
NC
WP
HOLD
NC
V
SS
Table 1. Pin Definitions
Pin Name
CS
SCK
SI
SO
WP
HOLD
HSB
I/O Type
Input
Input
Input
Output
Input
Input
Input/Output
Description
Chip select. Activates the device when pulled LOW. Driving this pin high puts the device in low
power standby mode.
Serial clock. Runs at speeds up to maximum of f
SCK
. Serial input is latched at the rising edge of
this clock. Serial output is driven at the falling edge of the clock.
Serial input. Pin for input of all SPI instructions and data.
Serial output. Pin for output of data through SPI.
Write protect. Implements hardware write protection in SPI.
HOLD pin. suspends serial operation.
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (t
HHHD
) with standard output high current and then
weak internal pull up resistor keeps this pin HIGH (External pull up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No connect. It
must never be connected to V
SS
.
No connect: This pin is not connected to the die.
Ground
Power supply (2.7 V to 3.6 V)
The EXPOSED PAD on the bottom of 8-pin DFN package is not connected to the die. It is
recommended to connect the EXPOSED PAD to V
SS
. Thermal vias can be used to increase thermal
conductivity.
V
CAP
NC
V
SS
V
CC
EXPOSED
PAD
Power supply
No connect
Power supply
Power supply
No connect
Notes
1. HSB pin is not available in 8 DFN packages.
2. CY14B101Q1 part does not have V
CAP
pin and does not support AutoStore.
3. CY14B101Q2 part does not have WP pin
Document #: 001-50091 Rev. *H
Page 3 of 26
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CY14B101Q1
CY14B101Q2
CY14B101Q3
Device Operation
CY14B101Q1/CY14B101Q2/CY14B101Q3 is a 1 Mbit nvSRAM
memory with a nonvolatile element in each memory cell. All the
reads and writes to nvSRAM happen to the SRAM which gives
nvSRAM the unique capability to handle infinite writes to the
memory. The data in SRAM is secured by a STORE sequence
which transfers the data in parallel to the nonvolatile
QuantumTrap cells. A small capacitor (V
CAP
) is used to
AutoStore the SRAM data in nonvolatile cells when power goes
down providing power-down data security. The QuantumTrap
nonvolatile elements built in the reliable SONOS technology
make nvSRAM the ideal choice for secure data storage.
The 1 Mbit memory array is organized as 128 K words x 8 bits.
The memory is accessed through a standard SPI interface that
enables very high clock speeds up to 40 MHz with zero cycle
delay read and write cycles. This device supports SPI modes 0
and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as SPI slave.
The device is enabled using the Chip Select (CS) pin and
accessed through Serial Input (SI), Serial Output (SO), and
Serial Clock (SCK) pins.
This device provides the feature for hardware and software write
protection through the WP pin and WRDI instruction respectively
along with mechanisms for block write protection (1/4, 1/2, or full
array) using BP0 and BP1 pins in the status register. Further, the
HOLD pin can be used to suspend any serial communication
without resetting the serial sequence.
CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard
SPI opcodes for memory access. In addition to the general SPI
instructions for read and write, it provides four special
instructions which enable access to four nvSRAM specific
functions: STORE, RECALL, AutoStore Disable (ASDISB), and
AutoStore Enable (ASENB).
The major benefit of serial (SPI) nvSRAM over serial EEPROMs
is that all reads and writes to nvSRAM are performed at the
speed of SPI bus with zero cycle delay. Therefore, no wait time
is required after any of the memory accesses. The STORE and
RECALL operations need finite time to complete and all memory
accesses are inhibited during this time. While a STORE or
RECALL operation is in progress, the busy status of the device
is indicated by the Hardware STORE Busy (HSB) pin and also
reflected on the RDY bit of the Status Register.
The device is available in three different pin configurations that
enable the user to choose a part which fits in best in their appli-
cation
.
The feature summary is given in
Table 2.
Table 2. Feature Summary
Feature
WP
V
CAP
HSB
AutoStore
Power Up
RECALL
Hardware
STORE
Software
STORE
CY14B101Q1
Yes
No
No
No
Yes
No
Yes
CY14B101Q2
No
Yes
No
Yes
Yes
No
Yes
CY14B101Q3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
enables the user to perform infinite write operations. A write cycle
is performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, three bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
The device allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The SPI write cycle sequence is defined in the memory access
section of SPI Protocol Description.
SRAM Read
A read cycle is performed at the SPI bus speed and the data is
read out with zero cycle delay after the READ instruction is
executed. The READ instruction is issued through the SI pin of
the nvSRAM and consists of the READ opcode and 3 bytes of
address. The data is read out on the SO pin.
This device allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x0000 and the device continues to read.
The SPI read cycle sequence is defined in the memory access
section of SPI Protocol Description.
STORE Operation
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The device stores data to the
nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power-down; Software STORE,
activated by a STORE instruction; and Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated,
read/write
to
CY14B101Q1/CY14B101Q2/CY14B101Q3 is inhibited until the
cycle is completed
The HSB signal or the RDY bit in the Status register can be
monitored by the system to detect if a STORE or Software
RECALL cycle is in progress. The busy status of nvSRAM is
indicated by HSB being pulled LOW or RDY bit being set to ‘1’.
To avoid unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. However, software initiated STORE cycles are
performed regardless of whether a write operation has taken
place.
Document #: 001-50091 Rev. *H
Page 4 of 26
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CY14B101Q1
CY14B101Q2
CY14B101Q3
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap during
power-down. This STORE makes use of an external capacitor
(V
CAP
) and enables the device to safely STORE the data in the
nonvolatile memory when power goes down.
During normal operation, the device draws current from V
CC
to
charge the capacitor connected to the V
CAP
pin. When the
voltage on the V
CC
pin drops below V
SWITCH
during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the V
CAP
capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since the last
RECALL.
Note
If a capacitor is not connected to V
CAP
pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
specified in
AutoStore Disable (ASDISB) instruction
on page 13.
If AutoStore is enabled without a capacitor on the V
CAP
pin, the
device attempts an AutoStore operation without sufficient charge
to complete the STORE. This corrupts the data stored in the
nvSRAM and Status register. To resume normal functionality, the
WRSR instruction must be issued to update the nonvolatile bits
BP0, BP1 and WPEN in the Status Register.
Figure 3
shows the proper connection of the storage capacitor
(V
CAP
) for AutoStore operation. Refer to
DC Electrical Charac-
teristics
on page 15 for the size of the V
CAP
.
Note
CY14B101Q1 does not support AutoStore operation. The
user must perform Software STORE operation by using the SPI
STORE instruction to secure the data.
Note
For successfull last data byte STORE, a hardware store
should be initiated atleast one clock cycle after the last data bit
D0 is recieved.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for t
LZHSB
time after HSB pin returns HIGH.
The HSB pin must be left unconnected if not used.
Note
CY14B101Q1/CY14B101Q2 do not have HSB pin. RDY bit
of the SPI status register may be probed to determine the Ready
or Busy status of nvSRAM
Figure 3. AutoStore Mode
V
CC
0.1 uF
10 kOhm
V
CC
CS
V
CAP
V
CAP
V
SS
Software STORE Operation
Software STORE enables the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
by executing STORE instruction irrespective of whether a write
has been performed since the last NV operation.
A STORE cycle takes t
STORE
time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status register or the HSB pin may be polled to find the
Ready or Busy status of the nvSRAM. After the t
STORE
cycle time
is completed, the SRAM is activated again for read and write
operations.
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. A RECALL may be
initiated in two ways: Hardware RECALL, initiated on power-up;
and Software RECALL, initiated by a SPI RECALL instruction.
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared. Next, the nonvolatile information is transferred
into the SRAM cells. All memory accesses are inhibited while a
RECALL cycle is in progress. The RECALL operation does not
alter the data in the nonvolatile elements.
Hardware RECALL (Power-Up)
During power-up, when V
CC
crosses V
SWITCH
, an automatic
RECALL sequence is initiated which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power-Up RECALL cycle takes t
FA
time to complete and the
memory access is disabled during this time. HSB pin is used to
detect the Ready status of the device.
Hardware STORE and HSB Pin Operation
The HSB pin in CY14B101Q3 is used to control and
acknowledge STORE operations. If no STORE or RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, nvSRAM conditionally
initiates a STORE operation after t
DELAY
duration. An actual
STORE cycle starts only if a write to the SRAM has been
performed since the last STORE or RECALL cycle. Reads and
writes to the memory are inhibited for t
STORE
duration or as long
as HSB pin is LOW.
The HSB pin also acts as an open drain driver (internal 100 kΩ
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
Note
After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (t
HHHD
) with standard output high
current and then remains HIGH by an internal 100 kΩ pull-up
resistor.
Document #: 001-50091 Rev. *H
Software RECALL
Software RECALL enables the user to initiate a RECALL
operation to restore the content of nonvolatile memory on to the
SRAM. A Software RECALL is issued by using the SPI
instruction for RECALL.
A Software RECALL takes t
RECALL
time to complete during
which all memory accesses to nvSRAM are inhibited. The
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
Page 5 of 26
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