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EN25B16

16 Mbit Serial Flash Memory with Boot and Parameter Sectors

FEATURES

•

Single power supply operation

- Full voltage range: 2.7-3.6 volt

•

16 M-bit Serial Flash

- 16 M-bit/2048 K-byte/8192 pages

- 256 bytes per programmable page

•

High performance

- 100MHz clock rate

•

Low power consumption

- 5 mA typical active current

- 1

μA

typical power down current

•

Flexible Sector Architecture:

- Two 4-Kbyte, one 8-Kbyte, one 16-Kbyte,one

32-Kbyte, and thirty one 64-Kbyte sectors

•

Software and Hardware Write Protection:

- Write Protect all or portion of memory via

software

- Enable/Disable protection with WP# pin

•

High performance program/erase speed

Byte program time: 7µs typical

Page program time: 1.5ms typical

Sector erase time: 300 to 800ms typical

Chip erase time: 18 Seconds typical

•

Minimum 100K endurance cycle

•

Package Options

- 8 pins SOP 200mil body width

- 8 contact VDFN

- 8 pins PDIP

- 16 pin SOP 300mil body width

- All Pb-free packages are RoHS compliant

•

Commercial and industrial temperature

Range

GENERAL DESCRIPTION

The EN25B16 is a 16M-bit (2048K-byte) Serial Flash memory, with advanced write protection

mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to

256 bytes at a time, using the Page Program instruction.

The EN25B16 has thirty six sectors including thirty one sectors of 64KB, one sector of 32KB, one sector

of 16KB, one sector of 8KB and two sectors of 4KB. This device is designed to allow either single Sector

at a time or full chip erase operation. The EN25B16 can protect boot code stored in the small sectors for

either bottom or top boot configurations. The device can sustain a minimum of 100K program/erase cycles

on each sector.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. E, Issue Date: 2007/06/07

EN25B16

Figure.1 CONNECTION DIAGRAMS

8 - LEAD SOP / PDIP

8 - CONTACT VDFN

16 - LEAD SOP

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. E, Issue Date: 2007/06/07

EN25B16

Figure 2. BLOCK DIAGRAM

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. E, Issue Date: 2007/06/07

EN25B16

SIGNAL DESCRIPTION

Serial Data Input (DI)

The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be

serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK)

input pin.

Serial Data Output (DO)

The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from (shifted

out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.

Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI

Mode")

Chip Select (CS#)

The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is

deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices

power consumption will be at standby levels unless an internal erase, program or status register cycle is

in progress. When CS# is brought low the device will be selected, power consumption will increase to

active levels and instructions can be written to and data read from the device. After power-up, CS# must

transition from high to low before a new instruction will be accepted.

Hold (HOLD#)

The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought low,

while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored

(don’t care). The hold function can be useful when multiple devices are sharing the same SPI signals.

Write Protect (WP#)

The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in

conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status Register Protect

(SRP) bits, a portion or the entire memory array can be hardware protected.

Table 1. PIN Names

Symbol

CLK

CS#

WP#

HOLD#

Vcc

Vss

Pin Name

Serial Clock Input

Serial Data Input

Serial Data Output

Chip Enable

Write Protect

Hold Input

Supply Voltage (2.7-3.6V)

Ground

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. E, Issue Date: 2007/06/07

EN25B16

MEMORY ORGANIZATION

The memory is organized as:

2,097,152 bytes

Flexible Sector Architecture

Two 4-Kbyte, one 8-Kbyte, one 16-Kbyte,one 32-Kbyte, and thirty one 64-Kbyte sectors

Bottom or top boot configurations

8192 pages (256 bytes each)

Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or

Bulk Erasable but not Page Erasable.

Table 2a.

Bottom Boot Block Sector Architecture

Sector

SECTOR SIZE (KByte)

Address range

1F0000h – 1FFFFFh

1E0000h – 1EFFFFh

1D0000h – 1DFFFFh

1C0000h – 1CFFFFh

1B0000h – 1BFFFFh

1A0000h – 1AFFFFh

190000h – 19FFFFh

180000h – 18FFFFh

170000h – 17FFFFh

160000h – 16FFFFh

150000h – 15FFFFh

140000h – 14FFFFh

130000h – 13FFFFh

120000h – 12FFFFh

110000h – 11FFFFh

100000h – 10FFFFh

0F0000h – 0FFFFFh

0E0000h – 0EFFFFh

0D0000h – 0DFFFFh

0C0000h – 0CFFFFh

0B0000h – 0BFFFFh

0A0000h – 0AFFFFh

090000h – 09FFFFh

080000h – 08FFFFh

070000h – 07FFFFh

060000h – 06FFFFh

050000h – 05FFFFh

040000h – 04FFFFh

030000h – 03FFFFh

020000h – 02FFFFh

010000h – 01FFFFh

008000h – 00FFFFh

004000h – 007FFFh

002000h – 003FFFh

001000h – 001FFFh

000000h – 000FFFh

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. E, Issue Date: 2007/06/07