ES8288
Low Power Stereo Audio ADC
GENERAL DESCRIPTION
ES8288 is a high performance, low
power and low cost audio ADC. It
consists of 2-ch ADC, microphone
amplifier and auto level control.
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The device uses advanced multi-bit
delta-sigma modulation technique
to convert data between digital and
analog. The multi-bit delta-sigma
modulators make the device with
low sensitivity to clock jitter and low
out of band noise.
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FEATURES
ADC
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24-bit, 8 kHz to 96 kHz sampling frequency
95 dB dynamic range, 95 dB signal to noise ratio,
-85 dB THD+N
Stereo or mono microphone interface with
microphone amplifier
Auto level control and noise gate
2-to-1 analog input selection
1.8V to 3.3V operation
9 mW recording
2
I C or SPI uC interface
Low Power
System
256Fs, 384Fs, USB 12 MHz or 24 MHz
Master or slave serial port
I
2
S, Left Justified, DSP/PCM Mode
APPLICATIONS
•
Portable audio recording
ORDERING INFORMATION
ES8288 -40°C ~ +85°C
QFN-28
Revision 6.0
1
November 2016
Everest Semiconductor
ES8288
BLOCK DIAGRAM ..................................................................................... 3
28-PIN QFN AND PIN DESCRIPTIONS .................................................... 4
TYPICAL APPLICATION CIRCUIT ............................................................ 6
CLOCK MODES AND SAMPLING FREQUENCIES.................................. 6
MICRO-CONTROLLER CONFIGURATION INTERFACE ......................... 8
5.1 SPI ...................................................................................................... 8
5.2 2-wire .................................................................................................. 9
6 CONFIGURATION REGISTER DEFINITION .......................................... 10
6.1 Chip Control and Power Management .............................................. 11
6.1.1 Register 0 – Chip Control 1, Default 0000 0110 .......................... 11
6.1.2 Register 1 – Chip Control 2, Default 0001 1100 .......................... 11
6.1.3 Register 2 – Chip Power Management, Default 1100 0011 ......... 11
6.1.4 Register 3 – ADC Power Management, Default 1111 1100 ......... 12
6.1.5 Register 5 – Chip Low Power 1, Default 0000 0000.................... 12
6.1.6 Register 6 – Chip Low Power 2, Default 0000 0000.................... 12
6.1.7 Register 7 – Analog Voltage Management, Default 0111 1100 .... 12
6.1.8 Register 8 – Master Mode Control, Default 1000 0000 ............... 13
6.2 ADC Control ...................................................................................... 13
6.2.1 Register 9 – ADC Control 1, Default 0000 0000 .......................... 13
6.2.2 Register 10 – ADC Control 2, Default 0000 0000 ........................ 13
6.2.3 Register 11 – ADC Control 3, Default 0000 0110 ........................ 14
6.2.4 Register 12 – ADC Control 4, Default 0000 0000 ........................ 14
6.2.5 Register 13 – ADC Control 5, Default 0000 0110 ........................ 14
6.2.6 Register 14 – ADC Control 6, Default 0011 0000 ........................ 15
6.2.7 Register 15 – ADC Control 7, Default 0011 0000 ........................ 15
6.2.8 Register 16 – ADC Control 8, Default 1100 0000 ........................ 16
6.2.9 Register 17 – ADC Control 9, Default 1100 0000 ........................ 16
6.2.10 Register 18 – ADC Control 10, Default 0011 1000 ...................... 16
6.2.11 Register 19 – ADC Control 11, Default 1011 0000 ...................... 17
6.2.12 Register 20 – ADC Control 12, Default 0011 0010 ...................... 17
6.2.13 Register 21 – ADC Control 13, Default 0000 0110 ...................... 18
6.2.14 Register 22 – ADC Control 14, Default 0000 0000 ...................... 18
6.2.15 Register 43 – ADC Control 15, Default 0011 1000 ...................... 18
7 Digital Audio Interface .............................................................................. 19
8 ELECTRICAL CHARACTERISTICS ........................................................ 20
8.1 Absolute Maximum Ratings ............................................................... 20
8.2 Recommended Operating Conditions ............................................... 20
8.3 ADC Analog and Filter Characteristics and Specifications ................ 20
8.4 Power Consumption Characteristics ................................................. 21
8.5 Serial Audio Port Switching Specifications ........................................ 21
8.6 Serial Control Port Switching Specifications ...................................... 22
9 PACKAGE INFORMATION ...................................................................... 24
10
CORPOARATION INFORMATION ....................................................... 25
Revision 6.0
2
November 2016
1
2
3
4
5
Everest Semiconductor
ES8288
1 BLOCK DIAGRAM
DVDD PVDD DGND
AVDD AGND AVDD AGND
VREF VMID
mux
LIN1
LIN2
mic amp
micL+micR
LIN1-RIN1
LIN2-RIN2
mux
ADC ALC
mux
RIN1
RIN2
mic amp
micL+micR
LIN1-RIN1
LIN2-RIN2
mux
ADC ALC
Clock Manager
uC Interface
Serial Audio Data
MCLK
CE CCLK CDATA
ASDOUT LRCK DSDIN SCLK
Revision 6.0
3
November 2016
Everest Semiconductor
ES8288
2 28-PIN QFN AND PIN DESCRIPTIONS
CDATA
CCLK
RIN1
23
LIN1
28
27
26
25
24
MCLK
DVDD
PVDD
DGND
SCLK
DGND
LRCK
1
2
3
4
5
6
7
10
12
13
14
11
8
9
22
21
20
19
18
17
16
15
LIN2
NC
CE
RIN2
VMID
ADCVREF
AGND
AVDD
NC
NC
ASDOUT
AGND
NC
NC
NC
NC
Revision 6.0
NC
4
November 2016
Everest Semiconductor
ES8288
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
MCLK
DVDD
PVDD
DGND
SCLK
DGND
LRCK
ASDOUT
NC
NC
NC
NC
AGND
NC
NC
NC
AVDD
AGND
ADCVREF
VMID
RIN2
LIN2
RIN1
LIN1
NC
CE
CDATA
CCLK
I/O
I
Supply
Supply
Supply
I/O
I
I
O
NC
NC
NC
NC
Supply
NC
NC
NC
Supply
Supply
O
O
I
I
I
I
NC
I
I/O
I
DESCRIPTION
Master clock
Digital core supply
Digital IO supply
Digital ground (return path for both DVDD and PVDD)
Audio data bit clock
Connect to ground
ADC audio data left and right clock
ADC audio data
No connect
No connect
No connect
No connect
Analog ground
No connect
No connect
No connect
Analog supply
Analog ground
Decoupling capacitor
Decoupling capacitor
Right channel input 2
Left channel input 2
Right channel input 1
Left channel input 1
No connect
Control select or device address selection
Control data input or output
Control clock input
Revision 6.0
5
November 2016
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