FEATURES
System
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Low Power Mono Audio CODEC
DAC
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ES8374
High performance and low power multi-
bit delta-sigma audio ADC and DAC
I
2
S/PCM master or slave serial data port
Two pairs of analog input with
differential input option
Mono analog output
256/384Fs, USB 12/24 MHz, fractional
PLL for wide range of system clocks
Standard audio clock output
Sophisticated analog input and output
routing, mixing and gain
GPIO
I
2
C interface
24-bit, 8 to 96 kHz sampling frequency
95 dB signal to noise ratio, -85 dB
THD+N
1.25W@8Ω/5V or 1.8W@4Ω/4.2V
mono class D speaker driver
Dynamic range compression
Headphone and external mic detection
Pop and click noise suppression
Low Power
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3.3V to 5V operation
32 mW playback; 42 mW playback and
record
Low standby current
ADC
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24-bit, 8 to 96 kHz sampling frequency
95 dB signal to noise ratio, -85 dB
THD+N
Low noise pre-amplifier
Noise reduction filters
Auto level control (ALC) and noise gate
Support analog and digital microphone
Microphone bias
APPLICATIONS
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Car DV
IP Camera
DVR, NVR
Surveillance
ORDERING INFORMATION
ES8374 -40°C ~ +85°C
QFN-28
1
Everest Semiconductor
Confidential
ES8374
1. BLOCK DIAGRAM
DSDIN
ASDOUT
SCLK
DLRCK
CDATA
CCLK
CE
GPIO1
GPIO2
MCLK
Clock Mgr/PLL
IC
2
GPIO
I S/PCM
2
LIN2
LIN1
RIN1
RIN2
PGA
PGA
Mono
ADC
ADC ALC
DAC DRC
Noise Filter
Mono
DAC
Mixer
LIN2
LIN1
HP Driver
MONOOUT
Class D
Driver
Mic Bias
Analog Reference
Power Supply
SPKP
SPKN
MICBIAS
ADCVREF
DACVREF
VMID
DVDD
PVDD
DGND
AVDD
AGND
SPKVDD
SPKGND
Revision 9
2
September 2018
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
Confidential
ES8374
2. PIN OUT AND DESCRIPTION
RIN2
LIN2
RIN1
LIN1/DMIC_SDA
GPIO1
CE
CDATA
22
23
24
25
26
27
28
CCLK
MCLK
DGND
GPIO2
PVDD
DVDD
SCLK
1
2
3
4
5
6
7
ES8374
21
20
19
18
17
16
15
MICBIAS
VMID
ADCVREF
DACVREF
AGND
AVDD
MONOOUT
14
13
12
11
10
9
8
SPKP
SPKVDD
SPKGND
SPKN
DSDIN
LRCK
ASDOUT
NAME
MCLK
CDATA
CCLK
CE
GPIO1
GPIO2
ASDOUT
DSDIN
LRCK
SCLK
LIN1/DMIC_SDA
RIN1
LIN2
RIN2
MONOOUT
SPKP
SPKN
MICBIAS
ADCVRP
DACVRP
VMID
DVDD
PVDD
DGND
AVDD
AGND
SPKVDD
SPKGND
I/O
DI
DIO
DI
DI
DIO
DIO
DO
DI
DIO
DIO
AI
AI
AI
AI
AO
AO
AO
DESCRIPTION
Master clock
I
2
C data
I
2
C clock
I
2
C address
GPIO (digital mic clock, jack detect, PLL out, interrupt)
GPIO (PLL out, interrupt)
I
2
S/PCM serial data out
I
2
S/PCM serial data in
I
2
S/PCM left and right clock
I
2
S/PCM bit clock
Left analog input or digital mic data
Right analog input
Left analog input
Right analog input
Mono output
Positive speaker out
Negative speaker out
Mic bias
ADC reference filtering
DAC reference filtering
Common mode filtering
Digital core power supply
Digital IO power supply
Digital ground
Analog power supply
Analog ground
Speaker driver power supply
Speaker driver ground
Revision 9
3
September 2018
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
Confidential
ES8374
3. TYPICAL APPLICATION CIRCUIT
DOUT
DCLK
DMIC
1uF
1uF
1uF
24
23
22
Mic2P
Mic2N
MICBIAS
26
4
25
AGND
RIN1
PLLout/GPIO2
DMICLK/GPIO1
LIN1/DMIC-SDA
RIN2
LIN2
CPU/DSP
27
28
1
2
7
8
9
10
5
6
CE
CDATA
CCLK
MCL
K
BCLK
ASDOUT
DLRCK
ADSIN
PV
DD
DVDD
DGND
PGND
AVDD
AGND
16
1uF
17
21
1uF
20
19
18
15
*
*
AVDD
AGND
Everest
ES8374
MICBIAS
V
MID
ADCV
REF
DACV
REF
MICBIAS
1uF
AGND
1uF
AGND
1uF
AGND
MOUT_OUT
SPKVDD
SPKGND
SPKLN
PV
DD
DVDD
*
*
*
* *
0.1uF 0.1uF
AGND AGND
V
bat
3
29
AGND
13
12
11
*
AGND
1uF
AGND
14
SPKLP
MONOOUT
GND(SYS)
0R
Speaker
AGND
In the layout, chip is treated as an analog device
For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible
Additional parallel capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help
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4. CLOCK MODES AND SAMPLING FREQUENCIES
The device supports three types of clocking: standard audio clocks (256Fs, 384Fs, 512Fs, etc),
USB clocks (12/24 MHz), and an on-chip 22-bit fractional PLL clock.
According to the serial audio data sampling frequency (Fs), the device can work in two speed
modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges
from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz.
The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and
SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the
system clock with specific rates. In master mode, LRCK and SCLK are derived internally from
device master clock.
5. MICRO-CONTROLLER CONFIGURATION INTERFACE
The device supports standard I
2
C micro-controller configuration interface. External micro-
controller can completely configure the device through writing to internal configuration
registers.
I
2
C interface is a bi-directional serial bus that uses a serial data line (SDA) and a serial clock line
(SCL) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1.
Data are transmitted synchronously to SCL clock on the SDA line on a byte-by-byte basis. Each
bit in a byte is sampled during SCL high with MSB bit being transmitted firstly. Each transferred
Revision 9
4
September 2018
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
Confidential
ES8374
byte is followed by an acknowledge bit from receiver to pull the SDA low. The transfer rate of
this interface can be up to 400 kbps.
Figure 1 Data Transfer for I
2
C Interface
A master controller initiates the transmission by sending a “start” signal, which is defined as a
high-to-low transition at SDA while SCL is high. The first byte transferred is the slave address. It
is a seven-bit chip address followed by a RW bit. The chip address must be 001000x, where x
equals AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is
received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by
the RW bit. The master can terminate the communication by generating a “stop” signal, which is
defined as a low-to-high transition at SDA while SCL is high.
In I
2
C interface mode, the registers can be written and read. The formats of “write” and “read”
instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you
must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the
register.
Table 1 Write Data to Register in I
2
C Interface Mode
Chip Address
001000
AD0
R/W
0
ACK
Register Address
RAM
ACK
Data to be written
DATA
Table 2 Read Data from Register in I
2
C Interface Mode
Chip Address
001000
Chip Address
001000
AD0
AD0
R/W
0
R/W
1
ACK
ACK
Register Address
RAM
Data to be read
Data
6. DIGITAL AUDIO INTERFACE
The device provides many formats of serial audio data interface to the input of the DAC or
output from the ADC through LRCK, BCLK (SCLK) and DACDAT/ADCDAT pins. These formats are
I
2
S, left justified, right justified, DSP/PCM and TDM mode. DAC input DACDAT is sampled by the
Revision 9
5
September 2018
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
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