ESD5302N
ESD5302N
2-Lines, Uni-directional, Ultra-low Capacitance
Transient Voltage Suppressors
http//:www.sh-willsemi.com
Descriptions
The ESD5302N is an ultra-low capacitance TVS (Transient
Voltage Suppressor) array designed to protect high speed
data interfaces. It has been specifically designed to protect
sensitive electronic components which are connected to data
and transmission lines from over-stress caused by ESD
(Electrostatic Discharge).
The
ESD5302N
incorporates
two
pairs
of
ultra-low
DFN1006-3L (Bottom View)
capacitance steering diodes plus a TVS diode.
The ESD5302N may be used to provide ESD protection up to
±20kV
(contact
and
air
discharge)
according
to
IEC61000-4-2, and withstand peak pulse current up to 4A
(8/20μs) according to IEC61000-4-5.
The ESD5302N is available in DFN1006-3L package.
Standard products are Pb-free and Halogen-free.
Features
Stand-off voltage: 5V max.
Transient protection for each line according to
IEC61000-4-2 (ESD): ±20kV (contact and air discharge)
IEC61000-4-4 (EFT): 40A (5/50ns)
IEC61000-4-5 (surge): 4A (8/20μs)
Ultra-low capacitance: C
J
= 0.4pF typ.
Ultra-low leakage current: I
R
<1nA typ.
Low clamping voltage: V
CL
= 17. 5V @ I
PP
= 16A(TLP)
Solid-state silicon technology
Circuit diagram
2
1
3
*
3
3 = Device code
* = Month code ( A~Z)
Marking (Top View)
Applications
USB 2.0 and USB 3.0
HDMI 1.3 and HDMI 1.4
SATA and eSATA
DVI
IEEE 1394
PCI Express
Portable Electronics and Notebooks
1
Device
Order information
Package
Shipping
ESD5302N-3/TR DFN1006-3L 10000/Tape&Reel
Will Semiconductor Ltd.
Revision 1.4, 2014/01/02
ESD5302N
Absolute maximum ratings
Parameter
Peak pulse power (t
p
= 8/20μs)
Peak pulse current (t
p
= 8/20μs)
ESD according to IEC61000-4-2 air discharge
ESD according to IEC61000-4-2 contact discharge
Operation junction temperature
Lead temperature
Storage temperature
Symbol
P
pk
I
PP
V
ESD
T
J
T
L
T
STG
Rating
60
4
±20
±20
125
260
-55~150
Unit
W
A
kV
o
o
o
C
C
C
Electrical characteristics
(T
A
= 25
o
C, unless otherwise noted)
Parameter
Reverse maximum working voltage
Reverse leakage current
Reverse breakdown voltage
Forward voltage
Clamping voltage
1)
Dynamic resistance
1)
Clamping voltage
2)
Symbol
V
RWM
I
R
V
BR
V
F
V
CL
R
DYN
V
CL
I
PP
= 1A, t
p
= 8/20μs
I
PP
= 4A, t
p
= 8/20μs
V
R
= 0V, f = 1MHz
Junction capacitance
C
J
Pin1 or 2 to Pin3
V
R
= 0V, f = 1MHz
Between Pin1 and Pin2
Notes:
1)
2)
TLP parameter: Z
0
= 50
Ω
, t
p
= 100ns, t
r
= 2ns, averaging window from 60ns to 80ns. R
DYN
is calculated from 4A to
16A.
Non-repetitive current pulse, according to IEC61000-4-5.
Condition
Min.
Typ.
Max.
5.0
Unit
V
nA
V
V
V
Ω
V
RWM
= 5V
I
T
= 1mA
I
T
= 10mA
I
PP
= 16A, t
p
= 100ns
7.0
0.6
<1
8.0
0.9
17.5
0.53
100
9.0
1.2
11
15
0.40
0.25
0.65
0.40
V
V
pF
pF
Will Semiconductor Ltd.
2
Revision 1.4, 2014/01/02
ESD5302N
Typical characteristics
(T
A
= 25
o
C, unless otherwise noted)
110
100
90
80
70
60
50
40
30
20
10
0
Front time: T
1
= 1.25
T = 8
s
Time to half-value:
T
2
= 20
s
100
90
Current (%)
10
Peak pulse current (%)
T
2
0
5
T
T
1
10
15
20
25
Time (
s)
30
35
40
t
r
= 0.7~1ns
30ns
Time (ns)
60ns
t
8/20μs waveform per IEC61000-4-5
Contact discharge current waveform per IEC61000-4-2
0.50
C
J
- Junction capacitance (pF)
V
C
- Clamping voltage (V)
14
Pulse waveform: t
p
= 8/20
s
f = 1MHz
0.45
0.40
0.35
0.30
Between Pin1 and Pin2
Pin1 or 2 to Pin3
12
10
0.25
0.20
0
1
2
3
4
5
8
0
1
2
3
4
5
I
PP
- Peak pulse current (A)
V
R
- Reverse voltage (V)
Clamping voltage vs. Peak pulse current
1000
Capacitance vs. Reveres voltage
100
Peak pulse power (W)
% of Rated power
100
80
60
40
20
0
10
1
1
10
100
Pulse time (
s)
1000
0
25
50
75
100
o
125
150
T
A
- Ambient temperature ( C)
Non-repetitive peak pulse power vs. Pulse time
Will Semiconductor Ltd.
3
Power derating vs. Ambient temperature
Revision 1.4, 2014/01/02
ESD5302N
Typical characteristics
(T
A
= 25
o
C, unless otherwise noted)
ESD clamping
(+8kV contact discharge per IEC61000-4-2)
ESD clamping
(-8kV contact discharge per IEC61000-4-2)
20
18
TLP current (A)
16
14
12
10
8
6
4
2
0
-2
0
2
4
6
8
Z
0
= 50
t
r
= 2ns
t
p
= 100ns
10 12 14 16 18 20 22
TLP voltage (V)
TLP Measurement
Will Semiconductor Ltd.
4
Revision 1.4, 2014/01/02
ESD5302N
Package outline dimensions
DFN1006-3L
Top View
Bottom View
Side View
Symbol
A
A1
A3
D
E
b1
b2
L1
L2
e1
e2
0.95
0.55
0.10
0.20
0.20
0.40
Dimensions in millimeter
Min.
0.40
0.00
Typ.
-
-
0.125 REF
1.00
0.60
0.15
0.25
0.30
0.50
0.350 BSC
0.675 BSC
1.05
0.65
0.20
0.30
0.40
0.60
Max.
0.50
0.05
Recommend land pattern (Unit: mm)
Notes:
This recommended land pattern is for reference
purposes only. Please consult your manufacturing
group to ensure your PCB design guidelines are met.
Will Semiconductor Ltd.
5
Revision 1.4, 2014/01/02
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