ESD5311N
ESD5311N
1-Line, Bi-directional, Ultra-low Capacitance
Transient Voltage Suppressors
http//:www.willsemi.com
Descriptions
The ESD5311N is an ultra-low capacitance TVS (Transient
Voltage Suppressor) designed to protect high speed data
interfaces. It has been specifically designed to protect
sensitive electronic components which are connected to data
and transmission lines from over-stress caused by ESD
(Electrostatic Discharge).
The ESD5311N incorporates one pair of ultra- low
capacitance steering diodes plus a TVS diode.
The ESD5311N may be used to provide ESD protection up to
±20kV (contact discharge) according to IEC61000-4-2, and
withstand peak pulse current up to 4A (8/20μs) according to
IEC61000-4-5.
The ESD5311N is available in DFN1006-2L package.
Standard products are Pb-free and Halogen-free.
Pin configuration
Pin1
Pin2
DFN1006-2L (Bottom View)
Features
Stand-off voltage: 5V Max
Transient protection for each line according to
IEC61000-4-2 (ESD): ±20kV (contact discharge)
IEC61000-4-5 (surge): 4 A (8/20μs)
Ultra-low capacitance: C
J
= 0.25pF typ.
Ultra-low leakage current: I
R
< 1nA typ.
Low clamping voltage: V
CL
= 21V typ. @ I
PP
= 16A (TLP)
Solid-state silicon technology
8 = Device code
* = Month code ( A~Z)
Marking (Top View)
Pin1
8*
Pin2
Order information
Applications
Device
USB 2.0 and USB 3.0
HDMI 1.3 and HDMI 1.4
SATA and eSATA
DVI
IEEE 1394
PCI Express
Portable Electronics
Notebooks
ESD5311N-2/TR DFN1006-2L 10000/Tape&Reel
Package
Shipping
Will Semiconductor Ltd.
1
Revision 1.3, 2015/10/28
ESD5311N
Absolute maximum ratings
Parameter
Peak pulse power (t
p
= 8/20μs)
Peak pulse current (t
p
= 8/20μs)
ESD according to IEC61000-4-2 air discharge
ESD according to IEC61000-4-2 contact discharge
Operation junction temperature
Lead temperature
Storage temperature
Symbol
P
pk
I
PP
V
ESD
T
J
T
L
T
STG
Rating
84
4
±20
±20
125
260
-55~150
Unit
W
A
kV
o
o
o
C
C
C
Electrical characteristics
(T
A
=25
o
C, unless otherwise noted)
Parameter
Reverse maximum working voltage
Reverse leakage current
Reverse breakdown voltage
Clamping voltage
1)
1)
Symbol
V
RWM
I
R
V
BR
V
CL
R
DYN
V
CL
V
CL
Condition
Min.
Typ.
Max.
5.0
Unit
V
nA
V
V
Ω
V
V
RWM
= 5V
I
T
= 1mA
I
PP
= 16A, t
p
= 100ns
7.5
<1
9.0
21.0
0.7
100
10.0
Dynamic resistance
Clamping voltage
Clamping voltage
2)
V
ESD
= 8kV
I
PP
= 1A, t
p
= 8/20μs
I
PP
= 4A, t
p
= 8/20μs
V
R
= 0V, f = 1MHz
Any I/O pin to GND
21
14
21
0.25
0.4
3)
V
V
pF
Junction capacitance
Notes:
C
J
1) TLP parameter: Z
0
= 50Ω , t
p
= 100ns, t
r
= 2ns, averaging window from 60ns to 80ns. R
DYN
is calculated from 4A to
16A.
2)
3)
Contact discharge mode, according to IEC61000-4-2.
Non-repetitive current pulse, according to IEC61000-4-5.
Will Semiconductor Ltd.
2
Revision 1.3, 2015/10/28
ESD5311N
Typical characteristics
(T
A
=25
o
C, unless otherwise noted)
100
90
Front time: T
1
= 1.25
×
T = 8µs
Time to half-value:
T
2
= 20µs
Peak pulse current (%)
100
90
50
T
2
Current (%)
10
10
0
0
T
T
1
20
Time (µs)
30ns
t
r
= 0.7~1ns
60ns
t
Time (ns)
8/20μs waveform per IEC61000-4-5
Contact discharge current waveform per IEC61000-4-2
18
V
C
- Clamping voltage (V)
0.28
Pulse waveform: t
p
= 8/20µs
C
J
- Junction capacitance (pF)
16
14
12
10
1
2
3
I
PP
- Peak pulse current (A)
4
0.26
0.24
0.22
f = 1MHz
V
AC
= 50mV
0.20
-5
-4
-3
-2 -1 0 1 2 3
V
R
- Reverse voltage (V)
4
5
Clamping voltage vs. Peak pulse current
Capacitance vs. Reveres voltage
1000
100
Peak pulse power (W)
% of Rated power
100
80
60
40
20
10
1
0
1
10
100
Pulse time (µs)
1000
0
25
50
75
100
125
150
T
A
- Ambient temperature (
o
C)
Power derating vs. Ambient temperature
Non-repetitive peak pulse power vs. Pulse time
Will Semiconductor Ltd.
3
Revision 1.3, 2015/10/28
ESD5311N
ESD clamping
(+8kV contact discharge per IEC61000-4-2)
ESD clamping
(-8kV contact discharge per IEC61000-4-2)
20
16
12
8
4
0
-4
-8
-12
-16
-20
-25
TLP current (A)
Z
0
= 50Ω
t
r
= 2ns
t
p
= 100ns
-20 -15 -10 -5 0 5 10 15 20 25
TLP voltage (V)
TLP Measurement
Will Semiconductor Ltd.
4
Revision 1.3, 2015/10/28
ESD5311N
Package outline dimensions
DFN1006-2L
CATHODE MARKING
b
（Ⅰ）
E
L
（Ⅱ）
D
e
Bottom View
（Ⅲ）
Top View
（Ⅰ）
A
（Ⅱ）
Side View
Min.
A
A1
A3
D
E
b
L
e
0.95
0.55
0.20
0.45
0.30
0.00
A
1
Typ.
-
-
0.125 Ref.
1.00
0.60
0.25
0.50
0.65 Typ.
A
3
Max.
0.50
0.05
1.05
0.65
0.30
0.55
Recommend land pattern (Unit: mm)
0.55
0.30
0.60
0.85
1.40
Notes:
This recommended land pattern is for reference
purposes only. Please consult your manufacturing
group to ensure your PCB design guidelines are met.
Will Semiconductor Ltd.
5
Revision 1.3, 2015/10/28
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