User’s Guide
ET-UARTSWD Users Guide
Power Application Controller
s®
www.active-semi.com
Copyright © 2018 Active-Semi, Inc.
No portion of this document may be reproduced or reused in any form without Active-Semi’s prior written consent
ET-UARTSWD User’s Guide
®
Power Application Controller
C
ONTENTS
Contents ...............................................................................................................................................................2
Overview ..............................................................................................................................................................3
1.
ET-UARTSWD Resources ............................................................................................................................6
1.1
Provided Connectors ............................................................................................................................6
MIPI 10 Cortex Debug Connector:................................................................................................................6
MIPI20 Cortex Debug + ETM Connector: .....................................................................................................6
Legacy IDC 20 JTAG IDC Connector ...........................................................................................................6
1.2
1.3
1.4
1.5
1.6
Pinout and Signal Connectivity ............................................................................................................7
Power Input ..........................................................................................................................................8
LED’s ....................................................................................................................................................8
Jumpers................................................................................................................................................8
Input SWD / JTAG Connectors ............................................................................................................9
Serial Wire Debug (SWD) .............................................................................................................................9
MIPI 10 Cortex Debug Connector.................................................................................................................9
MIPI20 Cortex Debug + ETM Connector ......................................................................................................9
Legacy IDC 20 JTAG IDC Connector ........................................................................................................ 10
1.7
Output UART / SWD / JTAG Connectors ......................................................................................... 11
Serial Wire Debug (SWD) .......................................................................................................................... 11
Serial Communications .............................................................................................................................. 11
MIPI20 Cortex Debug + ETM Connector ................................................................................................... 11
2.
Typical ET-UARTSWD Setup .................................................................................................................... 12
About Active-Semi® .......................................................................................................................................... 13
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No portion of this document may be reproduced or reused in any form without Active-Semi’s prior written consent
ET-UARTSWD User’s Guide
®
Power Application Controller
O
VERVIEW
Active-Semi’s ET-UARTSWD isolated communications and debugging interface unifies two modules into one.
Traditionally, interfacing a PC Computer to any of Active-Semi’s PAC5xxx Evaluation Modules required one
module to enable UART based serial communications and a second module to allow for in-system debugging
and FLASH memory programing. The ET-UARTSWD modules allow for a single board to carry all pertinent
functions regarding these two interfacing methodologies, making Evaluation Module bring up much quicker
and efficient.
Figure 1: ET-UARTSWD Block Diagram
The module is in essence divided in two independently usable sections. One section handles all aspects of
serial communications, with the subsequent section taking care of all debugging and FLASH programming
resources.
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®
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2018-04-05
No portion of this document may be reproduced or reused in any form without Active-Semi’s prior written consent
ET-UARTSWD User’s Guide
®
Power Application Controller
To provide serial communications capability, a USB to UART FTDI chip is provided. Coupled with the user’s
PC Computer, this chip generates a Virtual COM Port. Said COM Port can then be used by the Graphical
User Interface (GUI) commonly used to drive the application residing within the different PAC5xxx Evaluation
Modules. In order to protect the PC Computer from the possible high voltages some of the PAC5xxx
evaluation modules operate with, isolation chips have been placed in between the computer and the target
board.
Figure 2: Typical Host To Target Connections Block Diagram
The ET-UARTSWD interfacing board was designed with the many SWD and JTAG interfaces available for
different ARM RISC32 cores. In order to service the great variety of debugger modules commercially
available (i.e. IAR’s I-JET, Segger’s J-LINK, etc.), different connectors have been incorporated. MIPI20,
MIPI10 and 4 pin header connectors are included at the debugger’s side. This allows the user to connect their
respective debugger module to the interface board through the debugger module’s factory provided ribbon
cable. Note that debuggers that already include isolation are not supported. The two isolation stages will not
work together.
On the target’s side, a MIPI20 and 4 pin header connector are provided to ensure connectivity with any of the
PAC5xxx Evaluation modules.
In between the host side and the target side, an isolator block has been provided. This ensures safety to both
the user as well as the PC/debugger module, when dealing with high voltage platforms. It is recommended for
any application running at anything higher than 24V to take advantage of the provided isolation feature.
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2018-04-05
No portion of this document may be reproduced or reused in any form without Active-Semi’s prior written consent
ET-UARTSWD User’s Guide
®
Power Application Controller
Active-Semi’s ET-UARTSWD isolated UART and SWD Debug module kit consists of the following:
•
•
•
ET-UARTSWD Evaluation module
USM Micro Cable (Qty = 1)
Four pin female/female header connector cable (Qty = 2)
Solution Benefits:
•
•
•
•
•
Ideal for interfacing into all PAC5xxx Evaluation Modules.
Provides access to both serial communications as well as in-system debugging and FLASH
programming.
Isolation protects user’s computer as well as any other external hardware (e.g.
debugger/programmer).
Power can be derived from the debugger module, or the computer’s USB port.
Schematics, BOM, Layout drawings available
The following sections provide information about the hardware features of Active-Semi’s ET-UARTSWD
turnkey solution.
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®
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No portion of this document may be reproduced or reused in any form without Active-Semi’s prior written consent
