ESMT
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
8 Mbit (1M x 8/512K x 16)
3V Only CMOS Flash Memory
1. FEATURES
Single supply voltage 2.7V-3.6V
Fast access time: 70/90 ns
1,048,576x8 / 524,288x16 switchable by
BYTE
pin
Compatible with JEDEC standard
- Pin-out, packages and software commands
compatible with single-power supply Flash
Low power consumption
- 7mA typical active current
- 25uA typical standby current
100,000 program/erase cycles typically
20 years data retention
Command register architecture
- Byte programming (9us typical)
- Sector Erase(sector structure: one 16 KB, two 8 KB,
one 32 KB, and fifteen 64 KB)
Auto Erase (chip & sector) and Auto Program
- Any combination of sectors can be erased
concurrently; Chip erase also provided.
- Automatically program and verify data at specified
address
Erase Suspend/Erase Resume
- Suspend or Resume erasing sectors to allow the
read/program in another sector
Ready/Busy (RY/
BY
)
- RY/
BY
output pin for detection of program or erase
operation completion
End of program or erase detection
- Data polling
- Toggle bits
Hardware reset
- Hardware pin(
RESET
) resets the internal state machine
to the read mode
Sector Protection /Unprotection
- Hardware Protect/Unprotect any combination of sectors
from a program or erase operation.
Low V
CC
Write inhibit is equal to or less than 2.0V
Boot Sector Architecture
- U = Upper Boot Block
- B = Bottom Boot Block
Packages available:
- 48-pin TSOPI
- All Pb-free products are RoHS-Compliant
2. ORDERING INFORMATION
Part No
F49L800UA-70TIG
F49L800BA-70TIG
Boot
Upper
Bottom
Speed
70 ns
70 ns
Package
TSOPI
TSOPI
Comments
Pb-free
Pb-free
Part No
F49L800UA-90TIG
Boot
Upper
Speed
90 ns
90 ns
Package
TSOPI
TSOPI
Comments
Pb-free
Pb-free
F49L800BA-90TIG Bottom
3. GENERAL DESCRIPTION
The F49L800UA/F49L800BA is a 8 Megabit, 3V only
CMOS Flash memory device organized as 1M bytes of 8
bits or 512K words of 16bits. This device is packaged in
standard 48-pin TSOP. It is designed to be programmed
and erased both in system and can in standard EPROM
programmers.
With access times of 70 ns and 90 ns, the
F49L800UA/F49L800BA allows the operation of
high-speed microprocessors. The device has separate
chip enable
CE
, write enable
WE
, and output enable
OE
controls. ESMT's memory devices reliably store memory
data even after 100,000 program and erase cycles.
The F49L800UA/F49L800BA is entirely pin and
command set compatible with the JEDEC standard for 8
Megabit Flash memory devices. Commands are written to
the command register using standard microprocessor
write timings.
The F49L800UA/F49L800BA features a sector erase
architecture. The device memory array is divided into one
16 Kbytes, two 8 Kbytes, one 32 Kbytes, and fifteen 64
Kbytes. Sectors can be erased individually or in groups
without affecting the data in other sectors. Multiple-sector
erase and whole chip erase capabilities provide the
flexibility to revise the data in the device.
The sector protect/unprotect feature disables both
program and erase operations in any combination of the
sectors of the memory. This can be achieved in-system or
via programming equipment.
A low V
CC
detector inhibits write operations on loss of
power. End of program or erase is detected by the
Ready/Busy status pin, Data Polling of DQ7, or by the
Toggle Bit I feature on DQ6. Once the program or erase
cycle has been successfully completed, the device
internally resets to the Read mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2008
Revision: 1.2
1/47
ESMT
4. PIN CONFIGURATIONS
4.1
48-pin TSOP
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
GND
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
GND
CE
A0
F49L800U/BA
4.2
Pin Description
Symbol
Pin Name
Address Input
Data Input/Output
Q15 (Word mode) /
LSB addr (Byte Mode)
Chip Enable
Output Enable
Write Enable
Reset
Word/Byte selection input
Ready/Busy
Power Supply
Ground
No connection
Functions
To provide memory addresses.
To output data when Read and receive data when Write.
The outputs are in tri-state when OE or CE is high.
To bi-direction date I/O when
BYTE
is High
To input address when
BYTE
is Low
To activate the device when CE is low.
To gate the data output buffers.
To control the Write operations.
Hardware Reset Pin/Sector Protect Unprotect
To select word mode or byte mode
To check device operation status
To provide power
A0~A18
DQ0~DQ14
DQ15/A-1
CE
OE
WE
RESET
BYTE
RY/
BY
V
CC
GND
NC
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2008
Revision: 1.2
2/47
ESMT
5. SECTOR STRUCTURE
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
Sector Size
Byte Mode
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
32Kbytes
8Kbytes
8Kbytes
Word Mode
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
16Kwords
4Kwords
4Kwords
Address range
Byte Mode(x8)
00000H-0FFFFH
10000H-1FFFFH
20000H-2FFFFH
30000H-3FFFFH
40000H-4FFFFH
50000H-5FFFFH
60000H-6FFFFH
70000H-7FFFFH
80000H-8FFFFH
90000H-9FFFFH
A0000H-AFFFFH
B0000H-BFFFFH
C0000H-CFFFFH
D0000H-DFFFFH
E0000H-EFFFFH
F0000H-F7FFFH
F8000H-F9FFFH
FA000H-FBFFFH
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
Table 1: F49L800UA Sector Address Table
Sector Address
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
Word Mode(x16) A18 A17 A16 A15 A14 A13 A12
00000H-07FFFH
08000H-0FFFFH
10000H-17FFFH
18000H-1FFFFH
20000H-27FFFH
28000H-2FFFFH
30000H-37FFFH
38000H-3FFFFH
40000H-47FFFH
48000H-4FFFFH
50000H-57FFFH
58000H-5FFFFH
60000H-67FFFH
68000H-6FFFFH
70000H-77FFFH
78000H-7BFFFH
7C000H-7CFFFH
7D000H-7DFFFH
SA18
16Kbytes
8Kwords
FC000H-FFFFFH 7E000H-7FFFFH
1
Note: Byte Mode: address range A18:A-1, Word mode : address range A18:A0
Table 2: F49L800BA Sector Address Table
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
Sector Size
Byte Mode
16Kbytes
8Kbytes
8Kbytes
32Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
Word Mode
8Kwords
4Kwords
4Kwords
16Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
Address range
Byte Mode(x8)
00000H-03FFFH
04000H-05FFFH
06000H-07FFFH
08000H-0FFFFH
10000H-1FFFFH
20000H-2FFFFH
30000H-3FFFFH
40000H-4FFFFH
50000H-5FFFFH
60000H-6FFFFH
70000H-7FFFFH
80000H-8FFFFH
90000H-9FFFFH
A0000H-AFFFFH
B0000H-BFFFFH
C0000H-CFFFFH
D0000H-DFFFFH
E0000H-EFFFFH
F0000H-FFFFFH
00000H-01FFFH
02000H-02FFFH
03000H-03FFFH
04000H-07FFFH
08000H-0FFFFH
10000H-17FFFH
18000H-1FFFFH
20000H-27FFFH
28000H-2FFFFH
30000H-37FFFH
38000H-3FFFFH
40000H-47FFFH
48000H-4FFFFH
50000H-57FFFH
58000H-5FFFFH
60000H-67FFFH
68000H-6FFFFH
70000H-77FFFH
78000H-7FFFFH
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Sector Address
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Word Mode(x16) A18 A17 A16 A15 A14 A13 A12
Note: Byte Mode: address range A18:A-1, Word mode : address range A18:A0
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2008
Revision: 1.2
3/47
ESMT
6. FUNCTIONAL BLOCK DIAGRAM
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
BYTE
CE
OE
WE
RES ET
CONTROL
INPUT
LOGIC
PROGRAM / ERASE
HIGH VOLTAGE
WRITE
STATE
MACHING
(WSM)
STATE
REGISTER
F49L800U/BA
X-DECODER
A0~A18
ADDRESS
LATCH
AND
BUFFER
FLASH
ARRAY
ARRAY
SOURCE
HV
Y-PASS GATE
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
Y-DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
DQ0~DQ15(A-1)
I / O BUFFER
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2008
Revision: 1.2
4/47
ESMT
7. FUNCTIONAL DESCRIPTION
7.1 Device operation
This section describes the requirements and use
of the device bus operations, which are initiated
through the internal command register. The
register is composed of latches that store the
command, address and data information needed
to execute the command. The contents of the
F49L800UA/F49L800BA
Operation Temperature Condition -40
°
C~85
°
C
register serve as inputs to the internal state
machine. The state machine outputs dictate the
function of the device. The F49L800UA
/F49L800BA features various bus operations as
Table 3.
Table 3. F49L800UA/F49L800BA Operation Modes Selection
ADDRESS
DESCRIPTION
CE
OE
WE
RESET
A18 A11
DQ8~DQ15
A8
A5
DQ0~DQ7
BYTE
|
|
|
|
A9
A6
A1 A0
=V
IH
A12 A10
A7
A2
BYTE
=V
IL
High Z
DQ8~DQ14=
Reset(3)
Read
Write
Output Disable
Standby
Sector Protect(2)
Sector Unprotect(2)
Temporary sector unprotect
X
L
L
L
V
CC
±
0.3V
L
L
X
X
L
H
H
X
H
H
X
X
H
L
H
X
L
L
X
L, Vss±
0.3V(3)
H
H
H
V
CC
±
0.3V
V
ID
V
ID
V
ID
SA
SA
X
X
X
X
X
X
X
AIN
AIN
X
X
L
H
X
X
H
H
L
L
High Z
Dout
DIN
High Z
High Z
DIN
DIN
DIN
High Z
Dout
DIN
High Z
High Z
X
X
DIN
High Z
DQ15=A-1
High Z
High Z
X
X
High Z
AIN
See Table 4
Auto-select
Notes:
1.
L= Logic Low = V
IL
, H= Logic High = V
IH
, X= Don't Care, SA= Sector Address, V
ID
=10V to 10.5V.
AIN= Address In, DIN = Data In, Dout = Data Out.
2. The sector protect and unprotect functions may also be implemented via programming equipment.
3. See “Reset Mode” section.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2008
Revision: 1.2
5/47
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