Intel
®
Atom™ Processor C2000
Product Family for Microserver
Datasheet
January 2016
Order Number: 330061
-
003US
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Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet
2
January 2016
Order Number: 330061-003US
Revision History—C2000 Product Family
Revision History
Date
Revision
Description
The following technical changes were made in Datasheet 003US:
•
Table 1-2
- Added “Lowest Frequency Mode” row to table and removed “Reliability/
Availability” row from table.
•
Table 1-4
-
Added CPPM to terminology.
•
Section 3.3.1
and
Section 3.3.2
- Corrected minimum memory capacity. and device density.
•
Table 3-1
and
Table 3-2
- Added row for 1 GB.
•
Section 3.4.2
- Added Paragraph.
•
Section 4.4
-
Updated section.
•
Table 5-2
- Updated signals.
•
Section 7
- Added note to
SoC Reset and Power Supply Sequences.
•
Section 7.1.3
- Changed sequence shown in
V1P0A voltage is provided to all V1P0A voltage-
group pins the of SoC.
•
Section 7.2.1
-
Updated Cold Reset Sequence.
•
Section 12.3.6
-
Added note.
•
Section 15.4.7.1
and
Section 15.4.8.1-
Updated.
•
Table 22-3
-
Updated entries in Content column.
•
Section 22.7
-
Added note.
•
Table 23-2
- Updated descriptions.
•
Table 25-1
-
Updated and clarified reserved bits in
Section 25.3.1.
•
Figure 31-1
and
Table 31-14
-
Updated signal names.
•
Table 31-15
-
Updated RTC Well Signals.
•
Table 31-17
-
Updated Description of
PMU_RESETBUTTON_B/GPIOS_30.
•
Table 31-24
- Updated entries in “Internal Pull-up or Pull-down” column.
•
Table 31-25
- Updated entries in “Internal Pull-up or Pull-down” column.
•
Table 31-25
-
Added footnote to
SPI_CS0_B.
•
Table 33-2
and
Table 33-3
- Updated signal name of T
DQS_CK
.
•
Table 33-42
- Updated RTC Crystal Requirements.
•
Figure 33-10
- Figure updated.
The following technical changes were made in Datasheet 002US:
• Updated Revision numbering scheme for public release from 1.1 to 002US.
• Global Change - IRERR changed to IERR throughout the manual.
• Global Change - SMBALERT# changed to SMBALRT_N throughout the manual.
•
Table 1-2
- Added CUNIT_REG_DEVICEID[31:0] row.
•
Section 3.3.3
- Added System Memory Technology which is Not Supported.
•
Table 3-2
- Added Table note.
•
Section 7.2.1
- Updated V1P35S note.
•
Section 9.3
- Updated PCI Express.
•
Section 11.5.2.1
- Added paragraph.
•
Table 12-2
- Updated Description for FLEX_CLK_SE1.
•
Section 12.2
- Updated supported features.
•
Section 12.3.3.2
- Updated ASPM and ASPM Optionality.
•
Section 12.6
- Updated Power Management.
•
Table 12-9
- Added x4 Lanes with 4 Controllers SKUs.
• Previous Section 16.5.2 - Deleted section.
•
Table 16-1
- Changed Strap Usage for FLEX_CLK_SE1.
•
Table 16-5
- Updated Description for Bits 1 and 0.
•
Table 17-4
- Added Table Note 1 to Slave Address (Data Phase).
•
Table 31-6
- Updated Description for THERMTRIP_N.
•
Table 31-24
- Changed FLEX_CLK_SE1 pin 0 to Reserved.
•
Section 33.16.4
- Changed PPM Tolerance to 35 ppm.
•
Table 33-45
- Changed TRISE/FALL Min and Max Rise/Fall Time Max from 5ns to 3ns.
Initial Release.
January 2016
003US
September 2014
002US
January 2014
1.0
January 2016
Order Number: 330061-003US
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet
3
C2000 Product Family—Contents
Contents
Volume 1: C2000 Product Family Program Overview
..................... 30
1
Introduction and Product Offerings ......................................................................... 31
1.1
Overview ......................................................................................................... 31
1.2
Key Features.................................................................................................... 32
1.3
Intel
®
Atom™ Processor C2000 Product Family for Microserver Block
Diagram .......................................................................................................... 34
1.4
Product SKUs ................................................................................................... 35
1.5
Datasheet Volume Structure and Scope ............................................................... 36
1.6
Terminology..................................................................................................... 38
1.7
Related Documents ........................................................................................... 43
Multi-Core Intel
®
Atom™ Processors ....................................................................... 46
2.1
Signal Descriptions ........................................................................................... 46
2.2
Features .......................................................................................................... 46
2.3
SoC Components .............................................................................................. 47
2.3.1
SoC Core............................................................................................. 47
2.4
Features .......................................................................................................... 48
2.4.1
Intel
®
Virtualization Technology ............................................................. 48
2.4.2
Intel
®
VT-x Objectives .......................................................................... 48
2.4.2.1
Intel
®
VT-x Features ............................................................ 49
2.4.3
Security and Cryptography Technologies ................................................. 50
2.4.3.1
Advanced Encryption Standard New Instructions (AES-NI)......... 50
2.4.3.2
PCLMULQDQ Instruction ....................................................... 50
2.4.3.3
Digital Random Number Generator ......................................... 50
®
2.4.4
Intel Turbo Boost Technology............................................................... 51
2.4.4.1
Intel
®
Turbo Boost Technology Frequency............................... 51
2.5
CPUID Instruction and SoC Identification ............................................................. 52
Memory Controller................................................................................................... 57
3.1
Introduction ..................................................................................................... 57
3.2
Signal Descriptions ........................................................................................... 57
3.3
Features .......................................................................................................... 58
3.3.1
Supported Memory Configuration ........................................................... 58
3.3.2
System Memory Technology Supported ................................................... 58
3.3.3
System Memory Technology which is Not Supported ................................. 59
3.4
RAS Features ................................................................................................... 60
3.4.1
Data Parity Protection ........................................................................... 60
3.4.2
Memory Controller Error Correcting Codes (ECC) ...................................... 60
3.4.3
Demand and Patrol Scrubbing ................................................................ 62
3.4.4
DDR3 Data Scrambling.......................................................................... 62
System Agent and Root Complex ............................................................................. 63
4.1
Introduction ..................................................................................................... 63
4.2
Signal Descriptions ........................................................................................... 64
4.3
Features .......................................................................................................... 64
4.4
Root Complex................................................................................................... 65
4.4.1
Transaction Flow .................................................................................. 65
4.4.2
Root Complex Primary Transaction Routing .............................................. 66
4.5
Reliability, Availability and Serviceability (RAS) ..................................................... 67
4.6
Error Classification ............................................................................................ 68
4.6.1
Correctable Errors ................................................................................ 69
2
Volume 2: Functional
................................................................... 56
3
4
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet
4
January 2016
Order Number: 330061-003US
Contents—C2000 Product Family
4.7
4.8
4.9
4.10
4.11
4.12
5
Fatal Errors .......................................................................................... 69
Non-Fatal Errors ................................................................................... 69
4.6.3.1
Software Correctable Errors ................................................... 69
Global Error Reporting ....................................................................................... 70
4.7.1
Reporting Errors to CPU ......................................................................... 72
4.7.1.1
Non-Maskable Interrupt (NMI) ............................................... 72
4.7.1.2
System Management Interrupt (SMI) ...................................... 72
4.7.2
Reporting Global Errors to an External Device ........................................... 72
4.7.3
Machine Check Architecture.................................................................... 72
4.7.3.1
Machine Check Availability and Discovery ................................ 75
4.7.3.2
P5 Compatibility MSRs .......................................................... 75
4.7.3.3
Machine Check Global Control MSRs........................................ 76
4.7.3.4
Machine Check Error-Reporting MSR Banks 0-5 ........................ 77
4.7.4
Error-Status Cloaking Feature................................................................. 88
4.7.4.1
Hide Corrected-Error Status From OS...................................... 88
4.7.4.2
SMI for MCA Uncorrected Errors ............................................. 88
4.7.5
MCERR/IERR Signaling........................................................................... 89
4.7.6
PCI Express INTx and MSI...................................................................... 89
4.7.7
Error Register Overview ......................................................................... 90
4.7.7.1
Local Error Registers............................................................. 91
4.7.7.2
Global Error Registers ........................................................... 93
4.7.7.3
System Error (SERR) ............................................................ 95
4.7.7.4
First and Next Error Log Registers .......................................... 95
4.7.7.5
Error Register Flow ............................................................... 96
4.7.7.6
Error Counters ..................................................................... 97
SoC Error Handling Summary.............................................................................. 98
Register Map .................................................................................................. 105
System Agent Register Map .............................................................................. 106
4.10.1 Registers in Configuration Space ........................................................... 106
RAS Register Map............................................................................................ 107
4.11.1 Registers in Configuration Space ........................................................... 107
Root Complex Event Collector (RCEC) Register Map ............................................. 109
4.12.1 Registers in Configuration Space ........................................................... 109
4.6.2
4.6.3
Clock Architecture.................................................................................................. 111
5.1
Input Clocks ................................................................................................... 113
5.2
Output Clocks ................................................................................................. 114
Interrupt Architecture............................................................................................ 115
6.1
PCI Interrupts and Routing ............................................................................... 115
6.2
Non-Maskable Interrupt (NMI) .......................................................................... 118
6.3
System Management Interrupt (SMI) ................................................................. 118
6.4
System Control Interrupt (SCI) ......................................................................... 119
6.5
Message Signaled Interrupt (MSI and MSI-X) ...................................................... 119
6.6
I/O APIC Input Mapping ................................................................................... 120
6.7
8259 PIC Input Mapping................................................................................... 122
6.8
Device Interrupt-Generating Capabilities ............................................................ 123
SoC Reset and Power Supply Sequences ................................................................ 125
7.1
Power Up from G3 State (Mechanical Off) ........................................................... 125
7.1.1
While in the G3 State .......................................................................... 125
7.1.2
Powering-Up for the First Time ............................................................. 125
7.1.3
SUS Power Well Power-Up Sequence From the G3 State........................... 126
7.1.4
Core Power-Up Sequence ..................................................................... 129
7.2
Reset Sequences and Power-Down Sequences..................................................... 133
7.2.1
Cold Reset Sequence ........................................................................... 133
7.2.1.1
SUSPWRDNACK ................................................................. 138
6
7
January 2016
Order Number: 330061-003US
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet
5
