FM25256
256K-BIT SPI Serial EEPROM
With unique ID and Security Sector
Data Sheet
Jul. 2014
Data Sheet
FM25256 SPI Serial EEPROM
Ver1.0
1
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Shanghai Fudan Microelectronics Group Co., Ltd or its subsidiaries in China.
Shanghai Fudan Microelectronics Group Co., Ltd, Printed in the China, All Rights Reserved.
Data Sheet
FM25256 SPI Serial EEPROM
Ver.1.0
2
1. Description
The FM25256 provides 262,144 bits of serial
electrically erasable and programmable read-only
memory (EEPROM) organized as 32,768 words of
8 bits each, with 128-bit UID and 64-byte Security
Sector. The device is accessed through the SPI
bus, and is optimized for use in many industrial
and commercial applications where low-power and
low-voltage operations are essential.
4. Packaging Type
SOP 8
CS#
DO
WP#
VSS
1
2
3
4
8
7
6
5
VCC
HOLD#
CLK
DI
2. Features
Low Operation Voltage: V
CC
= 1.7V to 5.5V
Serial Peripheral Interface (SPI) compatible
Supports SPI Modes 0(0,0) and 3(1,1)
20MHz clock rate(4.5V~5.5V) and 5MHz
(1.7V)
64-byte Page Mode and Byte Write operation
supported
Block write protection
– Protect 1/4, 1/2, or entire array
Write Protect (WP#) pin and Write Disable
instructions for Hardware and Software Data
Protection
Lockable 64-Byte Security Sector
128-Bit Unique ID for each device
Self-timed Write Cycle (5 ms max)
High-reliability
– Endurance: 1,000,000 Write Cycles
– Data Retention: 40 Years
SOP8, TSSOP8 and UDFN8 Packages (RoHS
Compliant and Halogen-free)
TSSOP8
CS#
DO
WP#
VSS
1
2
3
4
8
7
6
5
VCC
HOLD#
CLK
DI
UDFN8
CS#
DO
WP#
VSS
1
2
3
4
8 VCC
7 HOLD#
6 CLK
5 DI
5. Absolute Maximum
Ratings
Operating Temperature
(Plastic Package)
Operating Temperature
(Module Package)
Storage Temperature
(Plastic Package)
Storage Temperature
(Module Package)
Voltage on Any Pin with
Respect to Ground
Maximum Operating
Voltage
DC Output Current
-55°C to +125°C
-20°C to +60°C
-65°C to +150°C
-25°C to +70°C
-1.0V to +7.0V
6.25V
5.0 mA
3. Pin Configurations
PIN
PIN
NO. NAME
1
CS#
2
DO
3
WP#
4
VSS
5
DI
6
CLK
7
HOLD#
8
VCC
I/O
I
O
I
I
I
I
FUNCTION
Chip Select Input
Data Output
Write Protect Input
Ground
Data Input
Serial Clock Input
Hold Input
Power Supply
*NOTICE: Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Data Sheet
FM25256 SPI Serial EEPROM
Ver.1.0
3
6.
Block Diagram
EN
DO
HV PUMP & TIMING
Data Register
And IO control
128-bit Status
UID Register
HV
DATA BUFFER
WP#
HOLD#
CS#
CONTROL
LOGIC
Data Memory
512P X 64B
CLK
DI
Address Register
and Counter
Security Sector (64 byte)
X DECODER
Figure 1 Block Diagram
Data Sheet
FM25256 SPI Serial EEPROM
Ver.1.0
4
7.
Pin Descriptions
Serial Clock (CLK):
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and
output operations.
Serial Data Input (DI):
The SPI Serial data input (DI) is used to serially receive write instructions,
addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin.
Serial Data Output (DO):
The SPI Serial data output (DO) is used to read data or status from the
device on the falling edge of CLK.
Chip Select (CS#):
The SPI Chip Select (CS#) pin enables and disables device operation.
When CS# is high, the device is deselected and the Serial Data Output (DO) pins are at high
impedance. When deselected, the devices power consumption will be at standby levels unless
an internal write cycle is in progress. When CS# is brought low, the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read
from the device. After power-up, CS# must transition from high to low before a new instruction
will be accepted.
HOLD (HOLD#):
The HOLD# pin allows the device to be paused while it is actively selected.
When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals
on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high, device
operation can resume. The HOLD# function can be useful when multiple devices are sharing the
same SPI signals. The HOLD# pin is active low.
Write Protect (WP#):
The Write Protect (WP#) pin is used in conjunction with the Status
Register Write Disable (SRWD) Bit to prevent the Status Registers from being written. Write
Protect (WP#) pin and Status Register Write Disable (SRWD) Bit enable the device to be put in
the Hardware Protected mode (when Status Register Write Disable (SRWD) Bit is set to 1, and
Write Protect (WP#) pin is driven low).
8.
Memory Organization
Table 1
Memory Organization
Page ADDR
0
1
2
···
511
xxxx x00x
xxxx xxxx
1
xxxx xx1x
xxxx xxxx
2
63
Byte Number
···
0
Instruction
0xh
Data Memory (512P X 64B)
8xh
83h
Security Sector (64 Bytes)
Unique ID(128 Bits)
Note:
1. Address bits A10A9 must be 00, A5~A0 define byte address, other bits are don’t care
2. Address bits A10A9 must be x1, A3~A0 define byte address, other bits are don’t care
Data Sheet
FM25256 SPI Serial EEPROM
Ver.1.0
5