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FTLC8221SCNM

光纤发射器、接收器、收发器 10x10G Parallel VCSEL, 10x10G PIN, OTN, 100GBASE-SR10 100m 100GbE, 112Gb/s, RoHS/lead free, multimode, CFP2, 3.3V, 6W, MPO receptacle, 0/70 C operation, 100m

器件类别:无线/射频/通信    光纤   

厂商名称:FINISAR

厂商官网:http://www.finisar.com/home.php

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
FINISAR
Reach Compliance Code
unknown
光纤设备类型
TRANSCEIVER
文档预览
Product Specification
100m Multi-rate 100GE CFP2 Optical Transceiver Module
FTLC8221SCNM
PRODUCT FEATURES
Hot-pluggable CFP2 form factor
Supports 103.1Gb/s and 112Gb/s
aggregate bit rates
Power dissipation < 4W
RoHS-6 compliant (lead-free)
Commercial case temperature range
of 0°C to 70°C
Single 3.3V power supply
Maximum link length of 100m on
OM3 Multimode Fiber (MMF) and
150m on OM4 MMF
Uncooled 10x10Gb/s 850nm
transmitter
CPPI electrical interface
Single MPO24 receptacle
MDIO management interface
Tx/Rx optical power monitoring
functionality
APPLICATIONS
100GBASE-SR10 Ethernet
10x11.2Gb/s Multimode OTN
2x 40GBASE-SR4 Ethernet
10x 10GE-SRLite Ethernet
Finisar’s FTLC8221SCNM 100GE CFP2 transceiver modules are designed for use in 100
Gigabit Ethernet links and 10x11.2G OTN client interfaces over multimode fiber. They
are compliant with the CFP2 MSA
1
and with IEEE 802.3ba 100GBASE-SR10
2
. Digital
diagnostics functions are available via the MDIO interface as specified by Finisar
Application Note AN-21xx
5
. The transceiver is RoHS-6 compliant and lead-free per
Directive 2011/65/EU
3
, and Finisar Application Note AN-2038
4
.
PRODUCT SELECTION
FTLC8221SCNM
S:
C:
N:
M:
OTU4 maximum bit rate (112 Gb/s)
10x10G parallel optics
Flat top module (no heat sink)
MPO receptacle
Finisar Corporation – 21-March-2016
Rev. B3
Page 1
FTLC8221SCNM Product Specification – March 2016
I.
Pin Descriptions
CFP2 ALT1 configuration, per CFP MSA
1
.
Top Row
GND
TX7n
TX7p
GND
TX6n
TX6p
GND
TX5n
TX5p
GND
TX4n
TX4p
GND
TX3n
TX3p
GND
TX2n
TX2p
GND
TX1n
TX1p
GND
TX0n
TX0p
GND
{REFCLKn}
Bottom Row
GND
TX9n
TX9p
GND
TX8n
TX8p
3.3V_GND
3.3V_GND
3.3V
3.3V
3.3V
3.3V
3.3V_GND
3.3V_GND
VND_IO_A
VND_IO_B
PRG_CNTL1
PRG_CNTL2
PRG_CNTL3
PRG_ALRM1
PRG_ALRM2
PRG_ALRM3
GND
TX_DIS
RX_LOS
Top Row
{REFCLKp}
GND
RX7n
RX7p
GND
RX6n
RX6p
GND
RX5n
RX5p
GND
RX4n
RX4p
GND
RX3n
RX3p
GND
RX2n
RX2p
GND
RX1n
RX1p
GND
RX0n
RX0p
GND
Bottom Row
MOD_ABS
MOD_RSTn
GLB_ALRMn
GND
MDC
MDIO
PRTADR0
PRTADR1
PRTADR2
VND_IO_C
VND_IO_D
VND_IO_E
3.3V_GND
3.3V_GND
3.3V
3.3V
3.3V
3.3V
3.3V_GND
GND
RX9n
RX9p
GND
RX8n
RX8p
GND
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
26 MOD_LOPWR
Finisar Corporation – 21-March-2016
Rev. B3
Page 2
FTLC8221SCNM Product Specification – March 2016
Bottom Row Pin Descriptions
PIN
Name
#
GND
1
2
TX9n
3
TX9p
GND
4
5
TX8n
6
TX8p
GND
7
3.3V_GND
8
3.3V
9
3.3V
10
3.3V
11
3.3V
12
3.3V_GND
13
3.3V_GND
14
VND_IO_A
15
VND_IO_B
16
PRG_CNTL1
17
PRG_CNTL2
18
PRG_CNTL3
19
20 PRG_ALRM1
21 PRG_ALRM2
22 PRG_ALRM3
GND
23
24
TX_DIS
25
RX_LOS
26 MOD_LOPWR
27
MOD_ABS
28
MOD_RSTn
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GLB_ALRMn
GND
MDC
MDIO
PRTADR0
PRTADR1
PRTADR2
VND_IO_C
VND_IO_D
VND_IO_E
3.3V_GND
3.3V_GND
3.3V
3.3V
3.3V
3.3V
3.3V_GND
GND
RX9n
RX9p
GND
RX8n
RX8p
GND
I/O
I
I
I
I
Logic
Lane #9 Transmitter pin (+)
Lane #9 Transmitter pin (-)
Lane #8 Transmitter pin (+)
Lane #8 Transmitter pin (-)
3.3V Module Supply Voltage Return Ground, internally connected to Signal Ground
3.3V Module Supply Voltage
3.3V Module Supply Voltage
3.3V Module Supply Voltage
3.3V Module Supply Voltage
3.3V Module Supply Voltage Return Ground, internally connected to Signal Ground
3.3V Module Supply Voltage Return Ground, internally connected to Signal Ground
Module Vendor I/O A. Do Not Connect!
Module Vendor I/O B. Do Not Connect!
LVCMOS w/ PUR Programmable Control 1 set over MDIO
LVCMOS w/ PUR Programmable Control 2 set over MDIO
LVCMOS w/ PUR Programmable Control 3 set over MDIO
LVCMOS
Programmable Alarm 1 set over MDIO
LVCMOS
Programmable Alarm 2 set over MDIO
LVCMOS
Programmable Alarm 3 set over MDIO
LVCMOS w/ PUR
LVCMOS
LVCMOS w/ PUR
GND
LVCMOS w/ PDR
LVCMOS
1.2V CMOS
1.2V CMOS
1.2V CMOS
1.2V CMOS
1.2V CMOS
Transmitter Disable for all lanes, "1" or NC = transmitter disabled, "0" = transmitter enabled
Receiver Loss of Optical Signal, "1": low optical signal, "0": normal condition
Module Low Power Mode. "1" or NC: module in low power (safe) mode, "0": power-on enabled
Module Absent. "1" or NC: module absent, "0": module present, Pull Up Resistor on Host
Module Reset. "0" resets the module, "1" or NC = module enabled, Pull Down Resistor in Module
Global Alarm. “0": alarm condition in any MDIO Alarm register, "1": no alarm condition, Open Drain,
Pull Up Resistor on Host
Management Data I/O bi-directional data (electrical specs as per 802.3ae and ba)
Management Data Clock (electrical specs as per 802.3ae and ba)
MDIO Physical Port address bit 0
MDIO Physical Port address bit 1
MDIO Physical Port address bit 2
Module Vendor I/O C. Do Not Connect!
Module Vendor I/O D. Do Not Connect!
Module Vendor I/O E. Do Not Connect!
3.3V Module Supply Voltage Return Ground, internally connected to Signal Ground
3.3V Module Supply Voltage Return Ground, internally connected to Signal Ground
3.3V Module Supply Voltage
3.3V Module Supply Voltage
3.3V Module Supply Voltage
3.3V Module Supply Voltage
3.3V Module Supply Voltage Return Ground, internally connected to Signal Ground
Lane #9 Receiver pin (+)
Lane #9 Receiver pin (-)
Lane #8 Receiver pin (+)
Lane #8 Receiver pin (-)
Description
I/O
I/O
I
I
I
O
O
O
I
O
I
O
I
O
I/O
I
I
I
I
I/O
I/O
I/O
O
O
O
O
Notes:
1. REFCLK is not required.
2. Tx_MCLK and Rx_MCLK functionality is not available in a CFP2 module with 10x10G electrical
I/O.
Finisar Corporation – 21-March-2016
Rev. B3
Page 3
FTLC8221SCNM Product Specification – March 2016
II.
Absolute Maximum Ratings
Module performance is not guaranteed beyond the operating range (see Section VI).
Exceeding the limits below may damage the transceiver module permanently.
Parameter
Maximum Supply Voltage
Storage Temperature
Case Operating Temperature
Relative Humidity
Receiver Damage Threshold, per Lane
Notes:
1.
Non-condensing.
Symbol
Vcc
T
S
T
OP
RH
P
Rdmg
Min
-0.5
-40
0
15
5.5
Typ
Max
4.0
85
70
85
Unit
V
C
C
%
dBm
Ref.
1
III.
Electrical Characteristics
(EOL, T
OP
= 0 to 70
C,
V
CC
= 3.13 to 3.47 Volts)
Symbol
Vcc
Icc
P
Min
3.13
Typ
Max
3.47
1.15
4.0
11.1810
4.0
1200
50
15
Per IEEE 802.3ba,
Section 86A.4.1.1
0.17
0.29
0.07
0.11, 0.31
95, 350
10.3125
-0.3
300
11.1810
4.0
800
7.5
5
Per IEEE 802.3ba,
Section 86A.4.2.1
Per IEEE 802.3ba,
Section 86A.4.2.2
0.42
0.65
0.29, 0.5
150, 425
Per CFP MSA
1
Unit
V
mA
W
Gb/s
V
mVpp
mV
mV
dB
UI
UI
UI
UI
mV
Gb/s
V
mVpp
mV
%
dB
dB
ps
UI
UI
UI
mV
mVpp
4
Ref.
Parameter
Supply Voltage
Supply Current
Module Total Power
Transmitter (per Lane)
Signaling rate per lane
Single ended input voltage tolerance
Differential data input swing
Differential input threshold
AC common mode input voltage tolerance
(RMS)
Differential input return loss
J2 Jitter Tolerance
J9 Jitter Tolerance
Data Dependent Pulse Width Shrinkage
Eye mask coordinates {X1, X2
Y1, Y2}
Receiver (per Lane)
Signaling rate per lane
Single-ended output voltage
Differential data output swing
AC common mode output voltage (RMS)
Termination mismatch at 1 MHx
Differential output return loss
Common mode output return loss
Output transition time, 20% to 80%
J2 Jitter output
J9 Jitter output
Eye mask coordinates {X1, X2
Y1, Y2}
Power Supply Ripple Tolerance
1
2
3
VinT
Vin,pp
10.3125
-0.3
120
Jt2
Jt9
DDPWS
5
2
6
Vout,pp
4
4
28
Jo2
Jo9
5
PSR
Finisar Corporation – 21-March-2016
Rev. B3
Page 4
FTLC8221SCNM Product Specification – March 2016
Notes:
1.
2.
3.
4.
5.
6.
Maximum total power value is specified across the full temperature and voltage range.
+/- 100ppm at 10.3125 Gb/s and +/-20ppm at 11.1810 Gb/s.
After internal AC coupling. Self-biasing 100 differential input.
10 MHz to 11.1 GHz range
Hit ratio = 5 x 10E-5
AC coupled with 100 differential output impedance. Limiting output.
FTLC8221SCNM Clocking Signals
Clock
Name
REFCLK
Status
Not Required
I/O
I
Value
Not required; terminated internally.
Finisar Corporation – 21-March-2016
Rev. B3
Page 5
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