1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
GD25LQ32D
DATASHEET
1
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
Contents
1.
2.
3.
4.
5.
6.
7.
FEATURES
.........................................................................................................................................................4
GENERAL DESCRIPTION
................................................................................................................................5
MEMORY ORGANIZATION
...............................................................................................................................7
DEVICE OPERATION
........................................................................................................................................8
DATA PROTECTION
..........................................................................................................................................9
STATUS REGISTER.........................................................................................................................................
11
COMMANDS DESCRIPTION
.......................................................................................................................... 13
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
7.13.
7.14.
7.15.
7.16.
7.17.
7.18.
7.19.
7.20.
7.21.
7.22.
7.23.
7.24.
7.25.
7.26.
7.27.
7.28.
7.29.
7.30.
7.31.
W
RITE
E
NABLE
(WREN) (06H) ................................................................................................................................ 17
W
RITE
D
ISABLE
(WRDI) (04H) ................................................................................................................................ 18
W
RITE
E
NABLE FOR
V
OLATILE
S
TATUS
R
EGISTER
(50H) ................................................................................................. 19
R
EAD
S
TATUS
R
EGISTER
(RDSR) (05H
OR
35H
OR
15H) .............................................................................................. 20
W
RITE
S
TATUS
R
EGISTER
(WRSR) (01H) ................................................................................................................... 21
R
EAD
D
ATA
B
YTES
(READ) (03H)............................................................................................................................. 22
R
EAD
D
ATA
B
YTES AT
H
IGHER
S
PEED
(F
AST
R
EAD
) (0BH) .............................................................................................. 22
F
AST
R
EAD
(0BH)
IN
QPI
MODE
............................................................................................................................... 23
D
UAL
O
UTPUT
F
AST
R
EAD
(3BH) .............................................................................................................................. 23
Q
UAD
O
UTPUT
F
AST
R
EAD
(6BH) ............................................................................................................................. 24
D
UAL
I/O F
AST
R
EAD
(BBH) .................................................................................................................................... 24
Q
UAD
I/O F
AST
R
EAD
(EBH) ................................................................................................................................... 26
Q
UAD
I/O W
ORD
F
AST
R
EAD
(E7H) ......................................................................................................................... 28
S
ET
B
URST WITH
W
RAP
(77H) ................................................................................................................................. 29
P
AGE
P
ROGRAM
(PP) (02H) .................................................................................................................................... 30
Q
UAD
P
AGE
P
ROGRAM
(32H) .................................................................................................................................. 31
S
ECTOR
E
RASE
(SE) (20H) ....................................................................................................................................... 33
32KB B
LOCK
E
RASE
(BE) (52H) ............................................................................................................................... 34
64KB B
LOCK
E
RASE
(BE) (D8H)............................................................................................................................... 35
C
HIP
E
RASE
(CE) (60/C7H) ..................................................................................................................................... 36
D
EEP
P
OWER
-D
OWN
(DP) (B9H) ............................................................................................................................. 37
R
ELEASE FROM
D
EEP
P
OWER
-D
OWN AND
R
EAD
D
EVICE
ID (RDI) (ABH) ......................................................................... 38
R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (REMS) (90H) ................................................................................................... 40
R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID D
UAL
I/O (92H) ................................................................................................. 41
R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID Q
UAD
I/O (94H)................................................................................................. 42
R
EAD
I
DENTIFICATION
(RDID) (9FH) ......................................................................................................................... 43
P
ROGRAM
/E
RASE
S
USPEND
(PES) (75H) ................................................................................................................... 44
P
ROGRAM
/E
RASE
R
ESUME
(PER) (7AH) ................................................................................................................... 45
R
EAD
U
NIQUE
ID (4BH) .......................................................................................................................................... 46
E
RASE
S
ECURITY
R
EGISTERS
(44H) ............................................................................................................................ 46
P
ROGRAM
S
ECURITY
R
EGISTERS
(42H) ....................................................................................................................... 47
2
1.8V Uniform Sector
Dual and Quad Serial Flash
7.32.
7.33.
7.34.
7.35.
7.36.
7.37.
8.
GD25LQ32D
R
EAD
S
ECURITY
R
EGISTERS
(48H) ............................................................................................................................. 48
S
ET
R
EAD
P
ARAMETERS
(C0H) ................................................................................................................................. 49
B
URST
R
EAD WITH
W
RAP
(0CH) ............................................................................................................................... 50
E
NABLE
QPI (38H)................................................................................................................................................. 50
D
ISABLE
QPI (FFH) ................................................................................................................................................ 51
E
NABLE
R
ESET
(66H)
AND
R
ESET
(99H) ..................................................................................................................... 52
LECTRICAL CHARACTERISTICS
................................................................................................................. 53
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
P
OWER
-O
N
T
IMING
................................................................................................................................................ 53
I
NITIAL
D
ELIVERY
S
TATE
........................................................................................................................................... 53
A
BSOLUTE
M
AXIMUM
R
ATINGS
................................................................................................................................. 53
C
APACITANCE
M
EASUREMENT
C
ONDITIONS
................................................................................................................. 54
DC CHARACTERISTICS......................................................................................................................................... 55
AC CHARACTERISTICS ......................................................................................................................................... 58
9.
ORDERING INFORMATION
............................................................................................................................ 62
9.1.
V
ALID
P
ART
N
UMBERS
............................................................................................................................................ 63
PACKAGE INFORMATION
......................................................................................................................... 65
P
ACKAGE
SOP8 208MIL ........................................................................................................................................ 65
P
ACKAGE
VSOP8 208MIL ...................................................................................................................................... 66
P
ACKAGE
USON8 (3*4
MM
).................................................................................................................................... 67
P
ACKAGE
USON8 (4*4
MM
,
THICKNESS
0.45
MM
) ...................................................................................................... 68
P
ACKAGE
WSON8 (6*5
MM
)................................................................................................................................... 69
REVISION HISTORY
.................................................................................................................................... 70
10.
10.1.
10.2.
10.3.
10.4.
10.5.
11.
3
1.8V Uniform Sector
Dual and Quad Serial Flash
1. FEATURES
◆
GD25LQ32D
32M-bit Serial Flash
- 4096K-Byte
- 256 Bytes per programmable page
◆
Fast Program/Erase Speed
- Page Program time: 0.7ms typical
- Sector Erase time: 90ms typical
- Block Erase time: 0.3/0.45s typical
◆
Standard, Dual, Quad SPI, QPI
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
- Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
- QPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆
- Chip Erase time: 20s typical
Flexible Architecture
- Uniform Sector of 4K-Byte
- Uniform Block of 32/64K-Byte
- Erase/Program Suspend/Resume
◆
High Speed Clock Frequency
- 120MHz for fast read with 30PF load
- Dual I/O Data transfer up to 240Mbits/s
- Quad I/O Data transfer up to 480Mbits/s
- QPI Mode Data transfer up to 480Mbits/s
◆
◆
Low Power Consumption
- 35uA typical stand-by current
- 1μA typical power down current
Advanced security Features
- 128-bit Unique ID for each device
- 3x1024-Byte Security Registers With OTP Lock
◆
Allows
XIP (execute in place) Operation
- Continuous Read With 8/16/32/64-byte Wrap
◆
Software/Hardware Write Protection
- Write protect all/portion of memory via software
- Enable/Disable protection with WP# Pin
- Top/Bottom Block protection
◆
Single Power Supply Voltage
- Full voltage range: 1.65~2.0V
◆
Minimum 100,000 Program/Erase Cycles
◆
Data Retention
- 20-year data retention typical
4
1.8V Uniform Sector
Dual and Quad Serial Flash
2. GENERAL DESCRIPTION
GD25LQ32D
The GD25LQ32D (32M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI and QPI mode: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#).
The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of
480Mbits/s.
CONNECTION DIAGRAM
CS#
SO
(IO1)
WP#
(IO2)
VSS
1
2
Top View
3
4
8
7
6
5
8–LEAD SOP
VCC
HOLD#
(IO3)
SCLK
SI
(IO0)
CS#
SO
(IO1)
WP#
(IO2)
1
2
Top View
3
8
VCC
7 HOLD#
(IO3)
6 SCLK
5
SI
(IO0)
VSS 4
8–LEAD
USON/WSON
PIN DESCRIPTION
Pin Name
CS#
SO (IO1)
WP# (IO2)
VSS
SI (IO0)
SCLK
HOLD# (IO3)
VCC
I/O
I
I/O
I/O
I
I/O
I/O
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
5
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