3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q32C
GD25Q32C
DATASHEET
1
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q32C
Contents
1.
2.
3.
4.
5.
6.
7.
FEATURES
................................................................................................................................................................ 4
GENERAL DESCRIPTION
...................................................................................................................................... 5
MEMORY ORGANIZATION
.................................................................................................................................... 7
DEVICE OPERATION
.............................................................................................................................................. 8
DATA PROTECTION
................................................................................................................................................ 9
STATUS REGISTER
............................................................................................................................................... 11
COMMANDS DESCRIPTION
............................................................................................................................... 13
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
7.13.
7.14.
7.15.
7.16.
7.17.
7.18.
7.19.
7.20.
7.21.
7.22.
7.23.
7.24.
7.25.
7.26.
7.27.
7.28.
7.29.
7.30.
7.31.
7.32.
W
RITE
E
NABLE
(WREN) (06H) ......................................................................................................................... 16
W
RITE
D
ISABLE
(WRDI) (04H) ......................................................................................................................... 16
W
RITE
E
NABLE FOR
V
OLATILE
S
TATUS
R
EGISTER
(50H) .................................................................................. 16
R
EAD
S
TATUS
R
EGISTER
(RDSR) (05H
OR
35H
OR
15H) .................................................................................. 17
W
RITE
S
TATUS
R
EGISTER
(WRSR) (01H
OR
31H
OR
11H) ................................................................................ 17
R
EAD
D
ATA
B
YTES
(READ) (03H) .................................................................................................................... 18
R
EAD
D
ATA
B
YTES AT
H
IGHER
S
PEED
(F
AST
R
EAD
) (0BH) .............................................................................. 19
D
UAL
O
UTPUT
F
AST
R
EAD
(3BH) ...................................................................................................................... 19
Q
UAD
O
UTPUT
F
AST
R
EAD
(6BH) ..................................................................................................................... 20
D
UAL
I/O F
AST
R
EAD
(BBH) ............................................................................................................................. 20
Q
UAD
I/O F
AST
R
EAD
(EBH) ............................................................................................................................. 22
Q
UAD
I/O W
ORD
F
AST
R
EAD
(E7H) .................................................................................................................. 23
S
ET
B
URST WITH
W
RAP
(77H) ........................................................................................................................... 25
P
AGE
P
ROGRAM
(PP) (02H) ............................................................................................................................... 26
Q
UAD
P
AGE
P
ROGRAM
(32H)............................................................................................................................. 27
F
AST
P
AGE
P
ROGRAM
(FPP) (F2H) .................................................................................................................... 28
S
ECTOR
E
RASE
(SE) (20H) ................................................................................................................................. 29
32KB B
LOCK
E
RASE
(BE) (52H) ....................................................................................................................... 29
64KB B
LOCK
E
RASE
(BE) (D8H) ...................................................................................................................... 30
C
HIP
E
RASE
(CE) (60/C7H) ............................................................................................................................... 30
D
EEP
P
OWER
-D
OWN
(DP) (B9H) ....................................................................................................................... 31
R
ELEASE FROM
D
EEP
P
OWER
-D
OWN OR
H
IGH
P
ERFORMANCE
M
ODE AND
R
EAD
D
EVICE
ID (RDI) (ABH)...... 32
R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (REMS) (90H)........................................................................................ 33
D
UAL
I/O R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (92H)...................................................................................... 34
Q
UAD
I/O R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (94H) ..................................................................................... 35
R
EAD
I
DENTIFICATION
(RDID) (9FH) ................................................................................................................ 36
H
IGH
P
ERFORMANCE
M
ODE
(HPM) (A3H) ........................................................................................................ 37
P
ROGRAM
/E
RASE
S
USPEND
(PES) (75H) ........................................................................................................... 37
P
ROGRAM
/E
RASE
R
ESUME
(PER) (7AH) ........................................................................................................... 38
E
RASE
S
ECURITY
R
EGISTERS
(44H) ................................................................................................................... 38
P
ROGRAM
S
ECURITY
R
EGISTERS
(42H).............................................................................................................. 39
R
EAD
S
ECURITY
R
EGISTERS
(48H)..................................................................................................................... 40
2
3.3V Uniform Sector
Dual and Quad Serial Flash
7.33.
7.34.
8.
GD25Q32C
E
NABLE
R
ESET
(66H)
AND
R
ESET
(99H) ............................................................................................................ 40
R
EAD
S
ERIAL
F
LASH
D
ISCOVERABLE
P
ARAMETER
(5AH) ................................................................................. 41
ELECTRICAL CHARACTERISTICS
................................................................................................................... 46
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
POWER-ON TIMING ....................................................................................................................................... 46
INITIAL DELIVERY STATE ........................................................................................................................... 46
DATA RETENTION AND ENDURANCE ...................................................................................................... 46
ABSOLUTE MAXIMUM RATINGS ............................................................................................................... 46
CAPACITANCE MEASUREMENT CONDITIONS ....................................................................................... 47
DC CHARACTERISTICS................................................................................................................................. 48
AC CHARACTERISTICS................................................................................................................................. 49
9.
10.
ORDERING INFORMATION
................................................................................................................................. 52
PACKAGE INFORMATION
............................................................................................................................... 53
P
ACKAGE
SOP8 208MIL ................................................................................................................................... 53
P
ACKAGE
VSOP8 208MIL................................................................................................................................. 54
P
ACKAGE
DIP8 300MIL .................................................................................................................................... 55
P
ACKAGE
WSON 8 (5*6
MM
) ............................................................................................................................. 56
P
ACKAGE
TFBGA-24BALL (6*4
BALL ARRAY
) ................................................................................................ 57
P
ACKAGE
TFBGA-24BALL (5*5
BALL ARRAY
) ................................................................................................ 58
P
ACKAGE
USON8 (3*3
MM
) ............................................................................................................................... 59
P
ACKAGE
USON8 (4*3
MM
) ............................................................................................................................... 60
P
ACKAGE
SOP8 150MIL ................................................................................................................................... 61
REVISION HISTORY
.......................................................................................................................................... 62
10.1.
10.2.
10.3.
10.4.
10.5.
10.6.
10.7.
10.8.
10.9.
11.
3
3.3V Uniform Sector
Dual and Quad Serial Flash
1. FEATURES
◆
GD25Q32C
32M-bit Serial Flash
-4096K-byte
-256 bytes per programmable page
◆
Program/Erase Speed
-Page Program time: 0.6ms typical
-Sector Erase time: 50ms typical
-Block Erase time: 0.15/0.25s typical
◆
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆
-Chip Erase time: 15s typical
Flexible Architecture
-Sector of 4K-byte
-Block of 32/64k-byte
◆
◆
Low Power Consumption
-20mA maximum active current
-1uA maximum power down current
High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 240Mbits/s
-Quad I/O Data transfer up to 480Mbits/s
-Continuous Read With 8/16/32/64-byte Wrap
◆
Advanced Security Features
(1)
-3*1024-Byte Security Registers With OTP Locks
-Discoverable parameters(SFDP) register
◆
Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top or Bottom, Sector or Block selection
◆
Single Power Supply Voltage
-Full voltage range:2.7~3.6V
◆
Package Information
-SOP8 (208mil)
-SOP8 (150mil)
-VSOP8 (208mil)
◆
Cycling endurance
-Minimum 100,000 Program/Erase Cycles
-DIP8 (300mil)
-WSON8 (5*6mm)
-USON8 (3*3mm)
◆
Data retention
-20-year data retention typical
-USON8 (4*3mm)
-TFBGA-24(6*4 ball array)
-TFBGA-24(5*5 ball array)
Note: 1.Please contact GigaDevice for details.
4
3.3V Uniform Sector
Dual and Quad Serial Flash
2. GENERAL DESCRIPTION
GD25Q32C
The GD25Q32C (32M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s.
CONNECTION DIAGRAM
CS#
SO
WP#
VSS
1
2
Top View
3
4
6
5
SCLK
SI
WP# 3
VSS 4
8–LEAD WSON/USON
8
7
VCC
HOLD#
CS#
SO
1
2
Top View
6 SCLK
5
SI
8
7
VCC
HOLD#
8–LEAD SOP/VSOP/DIP
PIN DESCRIPTION
Top View
Top View
4
NC
3
NC
2
NC
1
NC
NC
NC
NC
NC
NC
SCLK CS#
SO
NC
NC
2
NC
1
NC
A
B
C
D
E
24-BALL TFBGA
(6x4 ball array)
F
A
NC
NC
NC
E
SCLK CS#
SO
NC
VSS
NC
SI
NC
NC
3
NC
VSS
NC
SI
NC
VCC
WP# HOLD# NC
NC
4
NC
VCC
WP# HOLD# NC
5
NC
NC
NC
NC
NC
B
C
D
24-BALL TFBGA
(5x5 ball array)
Pin Name
CS#
SO (IO1)
WP# (IO2)
VSS
SI (IO0)
SCLK
HOLD# (IO3)
VCC
I/O
I
I/O
I/O
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
I/O
I
I/O
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
5
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