3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
GD25Q40C
DATASHEET
1
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
Contents
1.
2.
3.
4.
5.
6.
7.
FEATURES .................................................................................................................................................. 4
GENERAL DESCRIPTION .......................................................................................................................... 5
MEMORY ORGANIZATION ......................................................................................................................... 7
DEVICE OPERATION .................................................................................................................................. 8
DATA PROTECTION ................................................................................................................................... 9
STATUS REGISTER .................................................................................................................................. 11
COMMANDS DESCRIPTION .................................................................................................................... 13
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
W
RITE
E
NABLE
(WREN) (06H) ............................................................................................................. 16
W
RITE
D
ISABLE
(WRDI) (04H) .............................................................................................................. 16
R
EAD
S
TATUS
R
EGISTER
(RDSR) (05H
OR
35H)................................................................................... 17
W
RITE
S
TATUS
R
EGISTER
(WRSR) (01H) ............................................................................................. 17
W
RITE
E
NABLE FOR
V
OLATILE
S
TATUS
R
EGISTER
(50H) ........................................................................ 18
R
EAD
D
ATA
B
YTES
(READ) (03H) ........................................................................................................ 18
R
EAD
D
ATA
B
YTES AT
H
IGHER
S
PEED
(F
AST
R
EAD
) (0BH) ..................................................................... 19
D
UAL
O
UTPUT
F
AST
R
EAD
(3BH) .......................................................................................................... 19
Q
UAD
O
UTPUT
F
AST
R
EAD
(6BH) ......................................................................................................... 20
7.10. D
UAL
I/O F
AST
R
EAD
(BBH) ................................................................................................................. 20
7.11. Q
UAD
I/O F
AST
R
EAD
(EBH) ................................................................................................................. 22
7.12. Q
UAD
I/O W
ORD
F
AST
R
EAD
(E7H) ...................................................................................................... 23
7.13. S
ET
B
URST WITH
W
RAP
(77H) .............................................................................................................. 24
7.14. P
AGE
P
ROGRAM
(PP) (02H) ................................................................................................................. 24
7.15. Q
UAD
P
AGE
P
ROGRAM
(32H)................................................................................................................ 25
7.16. S
ECTOR
E
RASE
(SE) (20H) .................................................................................................................. 26
7.17. 32KB B
LOCK
E
RASE
(BE) (52H) ........................................................................................................... 27
7.18. 64KB B
LOCK
E
RASE
(BE) (D8H) .......................................................................................................... 27
7.19. C
HIP
E
RASE
(CE) (60/C7H) .................................................................................................................. 28
7.20. D
EEP
P
OWER
-D
OWN
(DP) (B9H) .......................................................................................................... 28
7.21. R
ELEASE FROM
D
EEP
P
OWER
-D
OWN OR
H
IGH
P
ERFORMANCE
M
ODE AND
R
EAD
D
EVICE
ID (RDI) (ABH) 29
7.22. R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (REMS) (90H) .............................................................................. 30
7.23. R
EAD
I
DENTIFICATION
(RDID) (9FH) ..................................................................................................... 31
7.24. H
IGH
P
ERFORMANCE
M
ODE
(HPM) (A3H) ............................................................................................. 31
7.25. C
ONTINUOUS
R
EAD
M
ODE
R
ESET
(CRMR) (FFH) ................................................................................. 32
7.26. R
EAD
U
NIQUE
ID (4BH) ........................................................................................................................ 33
7.27. P
ROGRAM
/E
RASE
S
USPEND
(PES) (75H) .............................................................................................. 33
7.28. P
ROGRAM
/E
RASE
R
ESUME
(PER) (7AH)............................................................................................... 34
7.29. E
RASE
S
ECURITY
R
EGISTERS
(44H) ...................................................................................................... 34
7.30. P
ROGRAM
S
ECURITY
R
EGISTERS
(42H) ................................................................................................. 35
7.31. R
EAD
S
ECURITY
R
EGISTERS
(48H)........................................................................................................ 36
7.32. E
NABLE
R
ESET
(66H)
AND
R
ESET
(99H) ............................................................................................... 36
2
3.3V Uniform Sector
Dual and Quad Serial Flash
8.
GD25Q40C
7.33. R
EAD
S
ERIAL
F
LASH
D
ISCOVERABLE
P
ARAMETER
(5AH) ........................................................................ 37
ELECTRICAL CHARACTERISTICS ......................................................................................................... 42
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
9.
POWER-ON TIMING .......................................................................................................................... 42
INITIAL DELIVERY STATE................................................................................................................. 42
ABSOLUTE MAXIMUM RATINGS ..................................................................................................... 42
CAPACITANCE MEASUREMENT CONDITIONS .............................................................................. 43
DC CHARACTERISTICS .................................................................................................................... 44
AC CHARACTERISTICS .................................................................................................................... 47
ORDERING INFORMATION ...................................................................................................................... 54
9.1.
V
ALID
P
ART
N
UMBERS
.......................................................................................................................... 55
PACKAGE INFORMATION .................................................................................................................... 57
10.
10.1. P
ACKAGE
SOP8 150MIL ...................................................................................................................... 57
10.2. P
ACKAGE
SOP8 208MIL ...................................................................................................................... 58
10.3. P
ACKAGE
TSSOP8 173MIL.................................................................................................................. 59
10.4. P
ACKAGE
DIP8 300MIL ........................................................................................................................ 60
10.5. P
ACKAGE
USON8 (3*2
MM
,
THICKNESS
0.45
MM
) .................................................................................... 61
10.6. P
ACKAGE
USON8 (3*4
MM
) ................................................................................................................... 62
11.
REVISION HISTORY.............................................................................................................................. 63
3
3.3V Uniform Sector
Dual and Quad Serial Flash
1. FEATURES
◆
4M-bit Serial Flash
-512K-byte
-256 bytes per programmable page
◆
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆
High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 240Mbits/s
-Quad I/O Data transfer up to 480Mbits/s
◆
Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top/Bottom block protection
◆
Minimum 100,000 Program/Erase Cycles
◆
Data Retention
-20-year data retention typical
◆
Low Power Consumption
◆
Flexible Architecture
-Uniform Sector of 4K-byte
-Uniform Block of 32/64K-byte
◆
Fast Program/Erase Speed
GD25Q40C
-Page Program time: 0.6ms typical
-Sector Erase time: 45ms typical
-Block Erase time: 0.15/0.25s typical
-Chip Erase time: 2.5s typical
-1μA typical deep power down current
-1μA typical standby current
◆
Advanced Security Features
-128-Bit Unique ID for each device
-4x256-Byte Security Registers With OTP Locks
-Serial Flash Discoverable Parameters (SFDP) Register
◆
Single Power Supply Voltage
-Full voltage range: 2.7~3.6V
◆
Allows XIP (execute in place) Operation
-Continuous Read With 8/16/32/64-byte Wrap
4
3.3V Uniform Sector
Dual and Quad Serial Flash
2. GENERAL DESCRIPTION
GD25Q40C
The GD25Q40C (4M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s.
CONNECTION DIAGRAM
CS#
SO/
IO1
WP#/
IO2
VSS
1
2
Top View
3
4
6
5
8
7
VCC
HOLD#/
IO3
SCLK
SI/
IO0
CS#
SO/
IO1
WP#/
IO2
VSS
1
2
Top View
3
4
8–LEAD WSON/USON
6
5
8
7
VCC
HOLD#/
IO3
SCLK
SI/
IO0
8–LEAD VSOP/SOP
PIN DESCRIPTION
Pin Name
CS#
SO (IO1)
WP# (IO2)
VSS
SI (IO0)
SCLK
HOLD# (IO3)
VCC
I/O
I
I/O
I/O
I
I/O
I/O
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
5
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